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Optimized operation scheme of flash-memory-based neural network online training with ultra-high endurance

Journal of Semico.ductors 2024年第1期45卷 33-37页

作者： Yang Feng Zhaohui Sun Yueran Qi Xuepeng Zhan Junyu Zhang Jing Liu Masaharu Kobayashi Jixuan Wu Jiezhi Chen School of Information Science and Engineering(ISE) Shandong UniversityQingdao 266200China neumem co. LtdHefei 230093China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics of Chinese Academy of SciencesBeijing 100084China Institute of Industrial Science The University of TokyoTokyoJapan

With the rapid development of machine learning,the demand for high-efficient co.puting beco.es more and more *** break the bottleneck of the traditional Von Neumann architecture,co.puting-in-memory(CIM)has attracted increasing attention in recent *** this work,to provide a feasible CIM solution for the large-scale neural networks(NN)requiring co.tinuous weight updating in online training,a flash-based co.puting-in-memory with high endurance(10^(9) cycles)and ultrafast programming speed is *** the one hand,the proposed programming scheme of channel hot electron injection(CHEI)and hot hole injection(HHI)demonstrate high linearity,symmetric potentiation,and a depression process,which help to improve the training speed and *** the other hand,the low-damage programming scheme and memory window(MW)optimizations can suppress cell degradation effectively with improved co.puting *** after 109 cycles,the leakage current(I_(off))of cells remains sub-10pA,ensuring the large-scale co.puting ability of *** characterizations are done on read disturb to demonstrate its robust *** processing CIFAR-10 tasks,it is evident that~90%accuracy can be achieved after 109 cycles in both ResNet50 and VGG16 *** results suggest that flash-based CIM has great potential to overco.e the limitations of traditional Von Neumann architectures and enable high-performance NN online training,which pave the way for further development of artificial intelligence(AI)accelerators.

关键词： NOR flash memory co.puting-in-memory endurance neural network online training

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Near-threshold-voltage operation in flash-based high-precision co.puting-in-memory to implement Poisson image editing

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Science China(Information Sciences) 2023年第12期66卷 261-266页

作者： Yang FENG Bing CHEN Mingfeng TANG Yueran QI Maoying BAI Chengcheng WANG Hai WANG Xuepeng ZHAN Junyu ZHANG Jing LIU Jixuan WU Jiezhi CHEN School of Information Science and Engineering Shandong University School of Micro-nano Electronics Zhejiang University neumem co. Ltd Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences

We propose a NOR flash-based co.puting-in-memory(CIM) to implement high-precision(32-bit) Poisson image editing, including the gradient operations and Laplace operation. To meet the requirements of image processing, CIM operation schemes and reliabilities are carefully studied and optimized,showing that the power co.sumption at the near-threshold-voltage(NTV) region can be as low as 40 fJ/bit,which is two orders lower than working at the saturation region. High-temperature retention, as well as various disturbs, are also analyzed. The proposed CIM scheme can be applied as an energy-efficient approach to co.struct the high-precision image processing accelerator.

关键词： NOR flash memory co.puting-in-memory variation Poisson image editing

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Flash-based in-memory co.puting for stochastic co.puting in image edge detection

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Journal of Semico.ductors 2023年第5期44卷 145-149页

作者： Zhaohui Sun Yang Feng Peng Guo Zheng Dong Junyu Zhang Jing Liu Xuepeng Zhan Jixuan Wu Jiezhi Chen School of Information Science and Engineering(ISE) Shandong UniversityQingdao 266000China Shandong Sinochip Semico.ductors co.Ltd Jinan 250101China neumem co. LtdHefei 230088China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics of Chinese Academy of SciencesBeijing 100029China

The“memory wall”of traditional von Neumann co.puting systems severely restricts the efficiency of data-intensive task execution,while in-memory co.puting(IMC)architecture is a promising approach to breaking the *** variations and instability in ultra-scaled memory cells seriously degrade the calculation accuracy in IMC architectures,stochastic co.puting(SC)can co.pensate for these shortco.ings due to its low sensitivity to cell ***,massive parallel co.puting can be processed to improve the speed and efficiency of the *** this paper,by designing logic functions in NOR flash arrays,SC in IMC for the image edge detection is realized,demonstrating ultra-low co.putational co.plexity and power co.sumption(25.5 fJ/pixel at 2-bit sequence length).More impressively,the noise immunity is 6 times higher than that of the traditional binary method,showing good tolerances to cell variation and reliability degradation when implementing massive parallel co.putation in the array.

关键词： in-memory co.puting stochastic co.puting NOR flash memory image edge detection

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