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Scaling trends in energy recovery logic:an analytical approach

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Journal of Semiconductors 2013年第8期34卷 79-83页

作者： Jitendra Kanungo S.Dasgupta Microelectronics & vlsi group Department of Electronics & Computer EngineeringIndian Institute of Technology

This paper presents an analytical model to study the scaling trends in energy recovery *** energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage,device threshold voltage and gate oxide *** proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the *** research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.

关键词： adiabatic logic energy efficient energy recovery logic low power digital CMOS logic

Modeling on oxide dependent 2DEG sheet charge density and threshold voltage in AlGaN/GaN MOSHEMT

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Journal of Semiconductors 2016年第4期37卷 44-49页

作者： J.Panda K.Jena R.Swain T.R.Lenka Microelectronics and vlsi Design group Department of Electronics and Communication Engineering National Institute of Technology Silchar

We have developed a physics based analytical model for the calculation of threshold voltage, two dimensional electron gas（2DEG） density and surface potential for Al Ga N/Ga N metal oxide semiconductor high electron mobility transistors（MOSHEMT）. The developed model includes important parameters like polarization charge density at oxide/Al Ga N and Al Ga N/Ga N interfaces, interfacial defect oxide charges and donor charges at the surface of the Al Ga N barrier. The effects of two different gate oxides（Al_2O_3 and HfO_2/ are compared for the performance evaluation of the proposed MOSHEMT. The MOSHEMTs with Al_2O_3 dielectric have an advantage of significant increase in 2DEG up to 1.2 10^（13） cm^2 with an increase in oxide thickness up to 10 nm as compared to HfO_2 dielectric MOSHEMT. The surface potential for HfO_2 based device decreases from 2 to –1.6 e V within10 nm of oxide thickness whereas for the Al_2O_3 based device a sharp transition of surface potential occurs from 2.8to –8.3 e V. The variation in oxide thickness and gate metal work function of the proposed MOSHEMT shifts the threshold voltage from negative to positive realizing the enhanced mode operation. Further to validate the model,the device is simulated in Silvaco Technology Computer Aided Design（TCAD） showing good agreement with the proposed model results. The accuracy of the developed calculations of the proposed model can be used to develop a complete physics based 2DEG sheet charge density and threshold voltage model for Ga N MOSHEMT devices for performance analysis.

关键词： 2DEG AlGaN GaN heterojunction MOSHEMT trap capacitance

Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator

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Journal of Semiconductors 2014年第9期35卷 97-103页

作者： Jitendra Kanungo S.Dasgupta Department of Electronics & Communication Engineering Jaypee University of Engineering & Technology Microelectronics & vlsi group Department of Electronics & Communication Engineering Indian Institute of Technology

We analyze the energy performance of a complete adiabatic circuit/system including the Power Clock Generator （PCG） at the 90 nm CMOS technology node. The energy performance in terms of the conversion efficiency of the PCG is extensively carried out under the variations of supply voltage, process comer and the driver transistor＇s width. We propose an energy-efficient singe cycle control circuit based on the two-stage comparator for the synchronous charge recovery sinusoidal power clock generator （PCG）. The proposed PCG is used to drive the 4-bit adiabatic Ripple Carry Adder （RCA） and their simulation results are compared with the adiabatic RCA driven by the reported PCG. We have also simulated the logically equivalent static CMOS RCA circuit to compare the energy saving of adiabatic and non-adiabatic logic circuits. In the clock frequency range from 25 MHz to 1GHz, the proposed PCG gives a maximum conversion efficiency of 56.48%. This research work shows how the design of an efficient PCG increases the energy saving of adiabatic logic.

关键词： clock-generator energy recovery logic low power single phase sinusoidal clock

Modeling and simulation of enhancement mode p-GaN Gate AlGaN/GaN HEMT for RF circuit switch applications

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Journal of Semiconductors 2017年第6期38卷 52-57页

作者： D.K.Panda T.R.Lenka Microelectronics and vlsi Design group Department of Electronics and Communication Engineering National Institute of Technology Silchar Assam 788010 India

An enhancement mode p-GaN gate AlGaN/GaN HEMT is proposed and a physics based virtual source charge model with Landauer approach for electron transport has been developed using Verilog-A and simulated using Cadence Spectre,in order to predict device characteristics such as threshold voltage,drain current and gate *** drain current model incorporates important physical effects such as velocity saturation,short channel effects like DIBL（drain induced barrier lowering）,channel length modulation（CLM）,and mobility degradation due to *** predicted Id–V（ds）,Id–V（gs）,and C–V characteristics show an excellent agreement with the experimental data for both drain current and capacitance which validate the *** developed model was then utilized to design and simulate a single-pole single-throw（SPST）RF switch.

关键词： CLM DIBL GaN HEMT SPST Verilog-A

Effect of metal-fingers/doped-ZnO transparent electrode on performance of GaN/InGaN solar cell

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Journal of Semiconductors 2017年第9期38卷 1-7页

作者： S.R.Routray T.R.Lenka Microelectronics and vlsi Design group Department of Electronics and Communication EngineeringNational Institute of Technology SilcharAssam788010India

The effect of doped-ZnO transparent conductive oxide （TCO） with metal （Ag）-fingers contact on GaN/InGaN solar cell is investigated through numerical simulations. An optical and electrical analysis of different dopant elements （such as B, A1, Ga, In and Sn） with ZnO as a top TCO layer is studied. A comparative analysis of metal square pad electrode, metal grid pattern electrode and metal-finger/ZnO type electrodes are taken into consideration to ensure the effect of anti-reflectivity by ZnO. The effect of thickness of ZnO and i-InGaN layer on performance of solar cell is also studied in detail. The proposed solar cell structure with Ag-fingers/ZnO：Al as top contact electrode shows interesting device characteristics compared to other dopants and metal top electrodes. The device achieves open circuit voltage -2.525 V, short circuit current -4.256 mA/cm^2, fill factor -87.86% and efficiency -9.22% under 1 Sun, air mass 1.5 global illumination.

关键词： Ag-finger/doped-ZnO TCO resistivity dopants GaN/InGaN solar cell

Small-signal model parameter extraction of E-mode N-polar GaN MOS-HEMT using optimization algorithms and its comparison

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Journal of Semiconductors 2018年第7期39卷 59-66页

作者： d.k.panda g.amarnath t.r.lenka microelectronics and vlsi design group department of electronics and communication engineeringnational institute of technology silcharAssam788010India

An improved small-signal parameter extraction technique for short channel enhancement-mode N-polar GaN MOS-HEMT is proposed, which is a combination of a conventional analytical method and optimization techniques. The extrinsic parameters such as parasitic capacitance, inductance and resistance are extracted under the pinch-off condition. The intrinsic parameters of the small-signal equivalent circuit（SSEC） have been extracted including gate forward and backward conductance. Different optimization algorithms such as PSO, Quasi Newton and Firefly optimization algorithm is applied to the extracted parameters to minimize the error between modeled and measured S-parameters. The different optimized SSEC models have been validated by comparing the S-parameters and unity current-gain with TCAD simulations and available experimental data from the literature. It is observed that the Firefly algorithm based optimization approach accurately extracts the small-signal model parameters as compared to other optimization algorithm techniques with a minimum error percentage of 1.3%.

关键词： Firefly GaN MOS-HEMT PSO SSEC TCAD

Gate leakage current reduction in IP3 SRAM cells at 45 nm CMOS technology for multimedia applications

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Journal of Semiconductors 2012年第5期33卷 88-92页

作者： R.K.Singh Neeraj Kr.Shukla Manisha Pattanaik Bipin Tripathi Kumaon Institute of Technology DwarahatAlmora(Uttarakhand)India ITM University Department of EECEGurgaon(Haryana)India ABV-IIITM VLSI GroupDepartment of ITGwalior(Madhya Pradesh)India

We have presented an analysis of the gate leakage current of the IP3 static random access memory （SRAM） cell structure when the cell is in idle mode（performs no data read/write operations） and active mode （performs data read/write operations）,along with the requirements for the overall standby leakage power,active write and read powers.A comparison has been drawn with existing SRAM cell structures,the conventional 6T,PP, P4 and P3 *** the supply voltage,V_（DD） = 0.8 V,a reduction of 98%,99%,92%and 94%is observed in the gate leakage current in comparison with the 6T,PP,P4 and P3 SRAM cells,respectively,while at V_（DD） = 0.7 V,it is 97%,98%,87%and 84%.A significant reduction is also observed in the overall standby leakage power by 56%〉, the active write power by 44%and the active read power by 99%,compared with the conventional 6T SRAM cell at V_（DD）= 0.8 V,with no loss in cell stability and performance with a small area *** simulation environment used for this work is 45 nm deep sub-micron complementary metal oxide semiconductor（CMOS） technology,t_（ox） = 2.4 nm,K_（thn） = 0.22 V,K_（thp） = 0.224 V,V_（DD） = 0.7 V and 0.8 V,at T = 300 K.

关键词： gate leakage subthreshold leakage low power deep sub-micron SRAM

Gradual refinement for application-specific MPSoC design from Simulink model to RTL implementation

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Journal of Zhejiang University-Science A(Applied Physics & Engineering) 2009年第2期10卷 151-164页

作者： Kai HUANG Xiao-lang YAN Sang-il HAN Soo-ik CHAE Ahmed A. JERRAYA Katalin POPOVICI Xavier GUERIN Lisane BRISOLARA Luigi CARRO Institute of vlsi Design Zhejiang University Hangzhou 310027 China Svstem Design group Seoul National University Seoul 151-744 Korea CEA-LETL Grenoble 38054 France SLS group.TIMA Laboratory Grenoble 38031. France Informatics Institute Federal University of Rio Grande do Sul. Porto Alegre 15064 Brazil

The application-specific multiprocessor system-on-chip(MPSoC) architecture is becoming an attractive solution to deal with increasingly complex embedded applications,which require both high performance and flexible programmability. As an effective method for MPSoC development,we present a gradual refinement flow starting from a high-level Simulink model to a synthesizable and executable hardware and software specification. The proposed methodology consists of five different abstract levels:Simulink combined algorithm and architecture model(CAAM),virtual architecture(VA),transactional accurate architecture(TA),virtual prototype(VP) and field-programmable gate array(FPGA) emulation. Experimental results of Motion-JPEG and H.264 show that the proposed gradual refinement flow can generate various MPSoC architectures from an original Simulink model,allowing processor,communication and tasks design space exploration.

关键词： Multiprocessor system-on-chip (MPSoC) design Refinement Simulink SystemC Motion-JPEG H.264

group delay and phase delay in GNSS systems

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Geo-Spatial Information Science 2013年第3期16卷 210-219页

作者： Reuben BERRY Philip G.MATTOS Izzet KALE Applied DSP and vlsi Research group Department of ElectronicsNetwork and Communications EngineeringUniversity of WestminsterLondonW1W 6UWUK STMicroelectronics R&D Ltd BristolBS324SQUK

GNSS signals have previously been modulated using binary phase shift keying but this modulation scheme is being replaced by binary offset carrier(BOC)*** has considered how the BOC signals might be affected differently when passed through a surface acoustic wave(SAW)*** concern has been that because of the split spectrum nature of the BOC signals,the upper and lower side-lobes will be delayed significantly *** was suggested because SAW filters have nonlinear phase characteristics and therefore different frequencies are delayed *** was suggested that this difference in delay will result in greater distortion of the correlation triangle.A delay magnification effect was also mentioned when analyzing the delay of a BOC *** was not understood why the theoretical delay calculations did not match up with the actual results in both hardware and *** paper clarifies some of the confusion and explains why the“delay magnification”applies to phase delay but not group *** paper also takes a look at how the code phase delay can vary with frequency and correlator spacing as a result of the SAW filter properties.

关键词： group delay phase delay SAW filter non-linear phase GNSS delay compensation