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A 10-bit 200-kS/s SAR ADC IP core for a touch screen SoC

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Journal of Semiconductors 2010年第10期31卷 121-125页

作者：佟星元杨银堂朱樟明盛文芳 institute of Microelectronics Xidian University Corp D.S. Semiconductor Manufacturing International Corporation

Based on a 5 MSBs （most-significant-bits）-plus-5 LSBs （least-significant-bits） C-R hybrid D/A conver sion and low-offset pseudo-differential comparison approach, with capacitor array axially symmetric layout topology and resistor string low gradient mismatch placement method, an 8-channel 10-bit 200-kS/s SAR ADC （successiveapproximation-register analog-to-digital converter） IP core for a touch screen SoC （system-on-chip） is implemented in a 0.18 μm 1P5M CMOS logic process. design considerations for the touch screen SAR ADC are included. With a 1.8 V power supply, the DNL （differential non-linearity） and INL （integral non-linearity） of this converter are measured to be about 0.32 LSB and 0.81 LSB respectively. With an input frequency of 91 kHz at 200-kS/s sampling rate, the spurious-free dynamic range and effective-number-of-bits are measured to be 63.2 dB and 9.15 bits respectively, and the power is about 136 μW. This converter occupies an area of about 0.08 mm^2. The design results show that it is very suitable for touch screen SoC applications.

关键词： analog-to-digital converter SAR touch screen SoC CMOS integrated circuits low power

Systolic B-1 Circuit in Galois Fields Based on a Quaternary Logic Technique

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Journal of Beijing institute of Technology 2020年第2期29卷 177-183页

作者： Haixia Wu Yilong Bai Tian Wang Xiaoran Li Long He School of Information and Electronics Beijing Institute of TechnologyBeijing 100081China

In order to improve the circuit complexity and reduce the long latency of B-1 operations,a novel B-1 operation in Galois Field GF(24)is presented and the corresponding systolic realization based on multiple-valued logic(MVL)is *** systolic structure employs multiplevalued current mode(MVCM)by using dynamic source-coupled logic(SCL)to reduce the initial delay and the transistor and wire *** performance is evaluated by HSPICE simulation in 0.18μm CMOS technology and a comparison is conducted between our proposed implementation and those reported in the *** initial delay and the sum of transistors and wires in our MVL design are about 43%and 13%lower,respectively,in comparison with other corresponding binary CMOS *** systolic architecture proposed is simple,regular,and modular,well suited for very large scale integration(VLSI)*** combination of MVCM circuits and relevant algorithms based on MVL seems to be a potential solution for high performance arithmetic operations in GF(2k).

关键词： multiple-valued logic(MVL) systolic B^-1 circuit Galois Fields

design of AB^2 in Galois Fields Based on Multiple-Valued Logic

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Journal of Beijing institute of Technology 2019年第4期28卷 764-769页

作者： Haixia Wu Long He Xiaoran Li Yilong Bai Minghao Zhang School of Information and Electronics Beijing Institute of TechnologyBeijing 100081China

A new AB^2 operation in Galois Field GF(24)is presented and its systolic realization based on multiple-valued logic(MVL)is *** systolic structure of the operation employs multiple-valued current mode(MVCM)by using dynamic source-coupled logic(SCL)to reduce the transistor and wire counts,and the initial *** performance is evaluated by HSPICE simulation with 0.18.μm CMOS technology.A comparison is conducted between our proposed implementation and those reported in the *** transistor counts,the wire counts and the initial delay in our MVL design show savings of about 23%,45%,and 72%,in comparison with the corresponding binary CMOS *** systolic architecture proposed is simple,regular,and modular,well suited for very large scale integration(VLSI)*** combination of MVCM circuits and relevant algorithms based on MVL seems to be a potential solution for high performance arithmetic operations in GF(2^k).

关键词： multiple-valued logic(MVL) AB^2 operation Galois Fields

Modeling Neuromorphic Persistent Firing Networks

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International Journal of Intelligence Science 2015年第2期5卷 89-101页

作者： Ning Ning Guoqi Li Wei He Kejie Huang Li Pan Kiruthika Ramanathan Rong Zhao Luping Shi Data Storage institute Agency for Science Technology and Research Singapore Department of Precision Instrument Tsinghua University Beijing China Center for Brain-Inspired Computing Research (CBICR) Tsinghua University Beijing China Singapore University of Technology and design Dover Singapore

Neurons are believed to be the brain computational engines of the brain. A recent discovery in neurophysiology reveals that interneurons can slowly integrate spiking, share the output across a coupled network of axons and respond with persistent firing even in the absence of input to the soma or dendrites, which has not been understood and could be very important for exploring the mechanism of human cognition. The conventional models are incapable of simulating the important newly-discovered phenomenon of persistent firing induced by axonal slow integration. In this paper, we propose a computationally efficient model of neurons through modeling the axon as a slow leaky integrator, which captures almost all-known neural behaviors. The model controls the switching of axonal firing dynamics between passive conduction mode and persistent firing mode. The interplay between the axonal integrated potential and its multiple thresholds in axon precisely determines the persistent firing dynamics of neurons. We also present a persistent firing polychronous spiking network which exhibits asynchronous dynamics indicating that this computationally efficient model is not only bio-plausible, but also suitable for large scale spiking network simulations. The implications of this network and the analog circuit design for exploring the relationship between working memory and persistent firing enable developing a spiking network-based memory and bio-inspired computer systems.

关键词： Neuron Model Neuromorphic Persistent Firing Slow Integration Spiking Network Working Memory

Deterministic Circular Self Test Path

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Tsinghua Science and Technology 2007年第S1期12卷 20-25页

作者：文科胡瑜李晓维 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences

Circular self test path (CSTP) is an attractive technique for testing digital integrated circuits(IC) in the nanometer era, because it can easily provide at-speed test with small test data volume and short test application time. However, CSTP cannot reliably attain high fault coverage because of difficulty of testing random-pattern-resistant faults. This paper presents a deterministic CSTP (DCSTP) structure that consists of a DCSTP chain and jumping logic, to attain high fault coverage with low area overhead. Experimental re- sults on ISCAS’89 benchmarks show that 100% fault coverage can be obtained with low area overhead and CPU time, especially for large circuits.

关键词： very large scale integration (VLSI) test built-in-self-test (BIST) circular self test path deterministic

design of House Keeping System for a Certain Micro Satellite

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High Technology Letters 2001年第4期7卷 69-72页

作者：马秀娟 Cao Xibin Xu Guodong Ma Xingrui Department of Information of Control Harbin Institute of Technology

This paper presents the design of hardware and software of the house keeping system for a certain micro satellite. The system uses micro electronic technique, large scale integrated circuits, processors and computers which has the advantages of strong function, high flexibility and reliability, It satisfies the requirements for efficient performance,light weight, small volume,and low consumption of power for micro satellite.

关键词： House keeping system Hardware structure Software design

A novel interconnect optimal buffer insertion model considering the self-heating effect

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Journal of Semiconductors 2013年第11期34卷 118-123页

作者：张岩董刚杨银堂王宁丁尧舜刘晓贤王凤娟 Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials Devices Microelectronics InstituteXidian University

Considering the self-heating effect, an accurate expression for the global interconnection resistance per unit length in terms of interconnection wire width and spacing is presented. Based on the proposed resistance model and according to the trade-off theory, a novel optimization analytical model of delay, power dissipation and bandwidth is derived. The proposed optimal model is verified and compared based on 90 nm, 65 nm and 40 nm CMOS technologies. It can be found that more optimum results can be easily obtained by the proposed model. This optimization model is more accurate and realistic than the conventional optimization models, and can be integrated into the global interconnection design ofnano-scale integrated circuits.

关键词： self-heating effect interconnection wire resistance per unit length optimal model very large scale integration

ASIC design of Floating-Point FFT Processor

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Journal of Beijing institute of Technology 2004年第4期13卷 389-393页

作者：陈禾赵忠武 School of Information Science and Technology Beijing Institute of Technology Beijing100081 China

An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.

关键词： application specific integrated circuit(ASIC) fast Fourier transform(FFT) floating-point pipeline very large scale integrated(VLSI)

Advanced mid-infrared plasmonic waveguides for on-chip integrated photonics

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Photonics Research 2023年第10期11卷 1694-1702页

作者： MAURO DAVID DAVIDE DISNAN ELENA ARIGLIANI ANNA LARDSCHNEIDER GEORG MARSCHICK HANH T.HOANG HERMANN DETZ BERNHARD LENDL ULRICH SCHMID GOTTFRIED STRASSER BORISLAV HINKOV institute of Solid State Electronics and Center for Micro-and Nanostructures TU WienViennaAustria institute of Sensor and Actuator Systems TU WienViennaAustria Central European institute of Technology Brno University of TechnologyBrnoCzech Republic institute of Chemical Technologies and Analytics ViennaAustria

Long-wave infrared(LWIR, 8–14 μm) photonics is a rapidly growing research field within the mid-IR with applications in molecular spectroscopy and optical free-space communication. LWIR applications are often addressed using rather bulky tabletop-sized free-space optical systems, preventing advanced photonic applications,such as rapid-time-scale experiments. Here, device miniaturization into photonic integrated circuits(PICs) with maintained optical capabilities is key to revolutionize mid-IR photonics. Subwavelength mode confinement in plasmonic structures enabled such miniaturization approaches in the visible-to-near-IR spectral range. However,adopting plasmonics for the LWIR needs suitable low-loss and-dispersion materials with compatible integration strategies to existing mid-IR technology. In this paper, we further unlock the field of LWIR/mid-IR PICs by combining photolithographic patterning of organic polymers with dielectric-loaded surface plasmon polariton(DLSPP) waveguides. In particular, polyethylene shows favorable optical properties, including low refractive index and broad transparency between ~2 μm and 200 μm. We investigate the whole value chain, including design, fabrication, and characterization of polyethylene-based DLSPP waveguides and demonstrate their first-time plasmonic operation and mode guiding capabilities along S-bend structures. Low bending losses of ~1.3 d B and straight-section propagation lengths of ~1 mm, pave the way for unprecedented complex on-chip mid-IR photonic devices. Moreover, DLSPPs allow full control of the mode parameters(propagation length and guiding capabilities) for precisely addressing advanced sensing and telecommunication applications with chip-scale devices.

关键词： waveguides transparency straight