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Hardware Acceleration for SLAM in Mobile Systems

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Journal of Computer Science & Technology 2023年第6期38卷 1300-1322页

作者：樊哲郝一帆支天郭崎杜子东 State Key Laboratory of Processors Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China School of Computer Science and Technology University of Chinese Academy of SciencesBeijing 100049China cambricon technologies Beijing 100191China

The emerging mobile robot industry has spurred a flurry of interest in solving the simultaneous localization and mapping(SLAM)***,existing SLAM platforms have difficulty in meeting the real-time and low-pow-er requirements imposed by mobile *** specialized hardware is promising with regard to achieving high per-formance and lowering the power,designing an efficient accelerator for SLAM is severely hindered by a wide variety of SLAM *** on our detailed analysis of representative SLAM algorithms,we observe that SLAM algorithms advance two challenges for designing efficient hardware accelerators:the large number of computational primitives and ir-regular control *** address these two challenges,we propose a hardware accelerator that features composable com-putation units classified as the matrix,vector,scalar,and control *** addition,we design a hierarchical instruction set for coping with a broad range of SLAM algorithms with irregular control *** results show that,com-pared against an Intel x86 processor,on average,our accelerator with the area of 7.41 mm^(2) achieves 10.52x and 112.62x better performance and energy savings,respectively,across different *** against a more energy-efficient ARM Cortex processor,our accelerator still achieves 33.03x and 62.64x better performance and energy savings,respec-tively.

关键词： hardware accelerator instruction set mobile system simultaneous localization and mapping(SLAM)algorithm

MW-DLA:a dynamic bit width deep learning accelerator

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High Technology Letters 2020年第2期26卷 145-151页

作者： Li Zhen Zhi Tian Liu Enhe Liu Shaoli Chen Tianshi Intelligent Processor Research Center Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190P.R.China University of Chinese Academy of Sciences Beijing 100049P.R.China cambricon technologies Corporation Limited Beijing 100191P.R.China

Deep learning algorithms are the basis of many artificial intelligence *** algorithms are both computationally intensive and memory intensive,making them difficult to deploy on embedded *** various deep learning accelerators(DLAs)are proposed and applied to achieve better performance and lower power ***,most deep learning accelerators are unable to support multiple data *** research proposes the MW-DLA,a deep learning accelerator supporting dynamic configurable *** work analyzes the data distribution of different data types in different layers and trains a typical network with per-layer *** a result,the proposed MW-DLA achieves 2X performance and more than 50%memory requirement for AlexNet with less than 5.77%area overhead.

关键词： deep learning accelerator(DLA) per-layer representation multiple-precision arithmetic unit

Assembly language and assembler for deep learning accelerators

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High Technology Letters 2019年第4期25卷 386-394页

作者： Lan Huiying Wu Linyang Han Dong Du Zidong Intelligent Processor Research Center Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190P.R.China University of Chinese Academy of Sciences Beijing 100049P.R.China cambricon technologies Corporation Limited Beijing 100191P.R.China

Deep learning accelerators(DLAs)have been proved to be efficient computational devices for processing deep learning *** DLA architectures are proposed and applied to different applications and ***,for most DLAs,their programming interfaces are either difficult to use or not efficient *** DLAs require programmers to directly write instructions,which is time-consuming and *** prevailing programming interface for DLAs is high-performance libraries and deep learning frameworks,which are easy to be used and very friendly to users,but their high abstraction level limits their control capacity over the hardware resources thus compromises the efficiency of the accelerator.A design of the programming interface is for *** various existing DLAs and their programming methods are analyzed and a methodology for designing programming interface for DLAs is proposed,which is a high-level assembly language(called DLA-AL),assembler and runtime for ***-AL is composed of a low-level assembly language and a set of high-level *** allows experienced experts to fully exploit the potential of DLAs and achieve near-optimal ***,by using DLA-AL,end-users who have little knowledge of the hardware are able to develop deep learning algorithms on DLAs spending minimal programming efforts.

关键词： deep learning deep learning accelerator(DLA) assembly language programming language

Optimizing deep learning inference on mobile devices with neural network accelerators

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High Technology Letters 2019年第4期25卷 417-425页

作者： Zeng Xi[[ Xu Yunlong Zhi Tian Intelligent Processor Research Center Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190P.R.China University of Chinese Academy of Sciences Beijing 100049P.R.China cambricon technologies Corporation Limited Beijing 100191P.R.China

Deep learning has now been widely used in intelligent apps of mobile *** pursuit of ultra-low power and latency,integrating neural network accelerators(NNA)to mobile phones has become a ***,conventional deep learning programming frameworks are not well-developed to support such devices,leading to low computing efficiency and high *** address this problem,a 2-stage pipeline is proposed for optimizing deep learning model inference on mobile devices with NNAs in terms of both speed and *** 1 st stage reduces computation workload via graph optimization,including splitting and merging *** 2 nd stage goes further by optimizing at compilation level,including kernel fusion and in-advance *** proposed optimizations on a commercial mobile phone with an NNA is *** experimental results show that the proposed approaches achieve 2.8×to 26×speed up,and reduce the memory-footprint by up to 75%.

关键词： machine learning inference neural network accelerator(NNA) low latency kernel fusion in-advance compilation

LACC:a hardware and software co-design accelerator for deep neural networks

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High Technology Letters 2021年第1期27卷 62-67页

作者： Yu Yong Zhi Tian Zhou Shengyuan State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190P.R.China School of Computer Science and Technology University of Chinese Academy of SciencesBeijing 100049P.R.China cambricon technologies Ltd Beijing 100190P.R.China

With the increasing of data size and model size,deep neural networks(DNNs)show outstanding performance in many artificial intelligence(AI)*** the big model size makes it a challenge for high-performance and low-power running DNN on processors,such as central processing unit(CPU),graphics processing unit(GPU),and tensor processing unit(TPU).This paper proposes a LOGNN data representation of 8 bits and a hardware and software co-design deep neural network accelerator LACC to meet the *** data representation replaces multiply operations to add and shift operations in running *** accelerator achieves higher efficiency than the state-of-the-art DNN accelerators by domain specific arithmetic computing ***,LACC speeds up the performance per watt by 1.5 times,compared to the state-of-the-art DNN accelerators on average.

关键词： deep neural network(DNN) domain specific accelerator domain specific data type

Memristor based onα-In_(2)Se_(3)for emulating biological synaptic plasticity and learning behavior

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Science China Materials 2022年第6期65卷 1631-1638页

作者： Ying Zhao Yifei Pei Zichang Zhang Xiaoyu Li Jingjuan Wang Lei Yan Hui He Zhenyu Zhou Jianhui Zhao Jingsheng Chen Xiaobing Yan Key Laboratory of brain-like neuromorphic devices and Systems of Hebei Province College of Electronic and Information EngineeringHebei UniversityBaoding 071002China cambricon technologies Corporation Limited Beijing 100000China Department of Materials Science and Engineering National University of SingaporeSingapore 117576Singapore

Nowadays,memristors are extremely similar to biological synapses and can achieve many basic functions of biological synapses,making them become a new generation of research hotspots for brain-like *** this work,we prepare a memristor based on two-dimensionalα-In_(2)Se_(3)nanosheets,which exhibits excellent electrical properties,faster switching speeds,and continuous tunability of device ***,most basic bio-synapse functions can be implemented faithfully,such as short-term memory(STM),long-term memory(LTM),four different types of spike-timing-dependent plasticity(STDP),and paired-pulse facilitation(PPF).More importantly,we systematically study three effective methods to achieve LTM,in which the reinforcement learning can be faithfully simulated according to the Ebbinghaus forgetting ***,we believe this work will promote the development of learning functions for brain-like computing and artificial intelligence.

关键词： memristors biological synapse learning behaviors 2D In_(2)Se_(3)