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Journal of Semiconductors 2011年第9期32卷 133-139页

作者：张正平王永禄黄兴发沈晓峰朱璨张磊余金山张瑞涛 No.24 Research Institute China Electronics Technology Group Corporation Science and Technology on analog Integrated Circuit Laboratory

A 2-Gsample/s 8-b analog-to-digital converter in 0.35μm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2 *** calibration technology is used for the offset and gain corrections of the S/H circuit,the offset correction of preamplifier,and the gain and clock phase corrections between *** a result of testing,the ADC achieves 7.32 ENOB at an analog input of 484 MHz and 7.1 ENOB at Nyquist input after the chip is self-corrected.

关键词： ultra high-speed interpolation algorithm folding analog-to-digital converter

A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology

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Journal of Semiconductors 2011年第1期32卷 108-115页

作者：余金山张瑞涛张正平王永禄朱璨张磊俞宙韩勇 National Laboratory of analog IC's 12th Institute of CETC School of Computer University of Defense Technology

A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital con- verter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.

关键词： ultra high-speed wide-bandwidth folding interpolating analog-to-digital converter

A 16 b 2 GHz digital-to-analog converter in 0.18 μm CMOS with digital calibration technology

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Journal of Semiconductors 2015年第10期36卷 93-99页

作者：杨卫东臧剑栋李铁虎罗璞蒲杰张瑞涛陈超 Science and Technology on analog Integrated Circuit Laboratory China Electronics Technology Group Corporation No.24 Research Institute

This paper presents a 16-bit 2 GSPS digital-to-analog converter （DAC） in 0.18/zm CMOS technology. This DAC is implemented using time division multiplex access system architecture in the digital domain. The input data is received with a two-channel LVDS interface. The DLL technology is introduced to meet the timing requirements between phases of the LVDS data and the data sampling clock. A FIFO is designed to absorb the phase difference between the data clock and DAC system clock. A delay controller is integrated to adjust the phase relationship between the high speed digital clock and analog clock, obtaining a sampling rate of 2 GSPS. The current source mismatch at higher bits is calibrated in the digital domain. Test results show that the DAC achieves 74.02 dBC SFDR at analog output of 36 MHz, and DNL less than ±2.1 LSB ＆ INL less than ±4.3 LSB after the chip is calibrated.

关键词： digital-to-analog converter (DAC) time-interleaving configuration delay lock loop (DLL) digitalcalibration

A NEW METHOD AND THEORETICAL ANALYSIS OF NUMERICAL analog OF SEMICONDUCTOR DEVICE

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Chinese Science Bulletin 1982年第7期27卷 790-795页

作者：袁益让丁兰英杨洪 Shandong Universty Jinan Shandong Universty Jinann the numerical analog of semiconductor device the mathematical model is a set nonlinear equations. The equation of carrier transport:

In the numerical analog of semiconductor device the mathematical model is a set nonlinear equations. The equation of carrier transport:

关键词： analog tward saturation 全一口甲甲加 illustrated downward lighting 口声

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analog Devices公司在大中国

电子产品世界 1997年第8期 144-10页

作者： Ben Nasker analog Devices公司东南亚区总经理

analog Devices公司涉足亚洲地区已有很多年,为我们的客户提供销售、市场、应用支持,同时也提供生产和测试设施.ADI(analog Devices,Inc.)的亚洲总部设在香港,旨在支持中国和香港特别行政区的广泛业务机遇,同时在韩国、新加坡、台湾和... 详细信息

analog Devices公司涉足亚洲地区已有很多年,为我们的客户提供销售、市场、应用支持,同时也提供生产和测试设施.ADI(analog Devices,Inc.)的亚洲总部设在香港,旨在支持中国和香港特别行政区的广泛业务机遇,同时在韩国、新加坡、台湾和印度班加罗尔设有销售办事处和应用中心.亚洲总部之所以专门设在香港,是因为我们坚信,无论是现在,还是在将来,中国和香港特别行政区都是电子工业发展最快的地区.

关键词：香港特别行政区解决方案中华人民共和国 analog Devices ADI

A 250MSPS 8-Bit analog-to-Digital Converter Based on 0.35μm BiCMOS Technology

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A 250MSPS 8-Bit Analog-to-Digital Converter Based on 0.35μm...

Preface to the Special Issue on Advanced analog and Mixed- Mode Integrated Circuits

2006 8th International Conference on Solid-State and Integrated Circuit Technology

作者： Yong-lu Wang Zhuo-yun Wang Shu-tao Zhou Kun-guang Xiao College of Physics Peking University National Laboratory of analog Integrated Circuits Sichuan Institute of Solid-State Circuits China Electronics Technology Group Corp.

ISBN: (纸本)1424401607

＜正＞An 8-bit 250MSPS flash A/D converter using 0.35μm BiCMOS process is presented in the paper.A novel sample-and-hold amplifier is used to improve sampling rate of the AiD converter,and the amount of input capacitors and equal resistor network is reduced by using an interpolating ***-input AND gate,latch and coding network are designed to overcome bubble and sparkle *** at 3.3V supply voltage,the A/D converter has a signal-to-noise ratio（SNR） of 47.3dB and it dissipates 561mW of power.

关键词： 8-bit Resistance Networks BiCMOS technology sampling rate AC to DC converters

来源： cnki会议评论

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cnki会议

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Journal of Semiconductors 2020年第11期41卷 1-1页

作者： Baoyong Chi Nan Sun Liyuan Liu Yan Lu Institute of Microelectronics Tsinghua UniversityBeijing100084China Department of Electrical Engineering Tsinghua UniversityBeijing100084China Institute of Semiconductors Chinese Academy of SciencesBeijing100083China State Key Laboratory of analog and Mixed-Signal VLSI University of MacaoMacaoChina

High performance analog and mixed signal circuits are strongly demanded in todays’system on chip *** found pervasive applications in A/D or D/A conversion,power management,radio frequency(RF)signal sensing and processing,clock generation,*** this special issue,we collected 7 comprehensive reviews and 2 research articles from leading research groups,which presented state-of-art design techniques and insight forecast of development trend in this hot area.

关键词： insight today Mixed

ENERGY DEPENDENCE OF ANGULAR DISTRIBUTIONS IN THE NON-analog PION DOUBLE CHARGE EXCHANGE REACTION

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Chinese Science Bulletin 1987年第1期32卷 12-14页

作者：马维兴王思问张高友陈崇光赵叔平 Institute of High Energy Physics Academia Sinica Beijing Department of Physics Northwest University Xi'an Graduate School of Academia Sinica Beijing Department of Physics University of Science and Technology of China Hefein pion double charge exchange (DCX) the existence of large non-analog cross section for (π~+ π~-) reaction on T=0 nuclei is a noticeable phenomenon. At 164 MeV the cross section for ~(16)O (T=0) is nearly as large as that for ~(18)O (T=1). For instance the ratio σ(~(18)O)/σ(~(16)O) is 3: 1 at 164 MeV but at 292 MeV it rapidly becomes 20:1. That means the ratios are strongly energy-dependent. The anomalous features observed in the ~(16)O

In pion double charge exchange （DCX）, the existence of large non-analog cross section for （π+, π-） reaction on T=0 nuclei is a noticeable phenomenon. At 164 MeV, the cross section for 16O （T=0） is nearly as large as that for 18O （T=1）. For instance, the ratio σ(18O)/σ(16O) is 3: 1 at 164 MeV, but at 292 MeV, it rapidly becomes 20:1. That means the ratios are strongly energy-dependent. The anomalous features observed in the

关键词： instance analog noticeable nuclei anomalous overlapping absolute expectation angular delta

Design of a high-performance PJFET for the input stage of an integrated operational amplifier

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Journal of Semiconductors 2010年第1期31卷 34-38页

作者：税国华唐昭焕王志宽欧红旗杨永晖刘勇王学毅 Sichuan Institute of Solid-State Circuits CETC National Laboratory of analog ICs National Laboratory of analog ICs Chongqing 400060 China

With Shockley＇s approximate-channel theory and TCAD tools, a high-voltage, ultra-shallow junction PJFET for the input stage of an integrated operational amplifier （OPA） was realized. The high-performance PJFET device was developed in the Bi-FET process technology. The measured specifications are as follows. The top-gate junction depth is about 0.1 μm, the gate-leakage current is less than 5 pA, the breakdown voltage is more than 80 V, and the pinch-off voltage is optional between 0.8 and 2.0 V. The device and its Bi-FET process technology were used to design and process a high input-impedance integrated OPA. The measured results show that the OPA has a bias current of less than 50 pA, voltage noise of less than 50 nV/Hz^1/2, and current noise of less than 0.05 pA/Hz^1/2.

关键词： PJFET operational amplifier Bi-FET process ultra-shallow junction high input-impedance

A novel structure in reducing the on-resistance of a VDMOS

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Journal of Semiconductors 2011年第2期32卷 44-47页

作者：杨永晖唐昭焕张正元刘勇王志宽谭开洲冯志成 Sichuan Institute of Solid-State Circuits CETC National Laboratory of analog ICs

A novel structure of a VDMOS in reducing on-resistance is proposed. With this structure, the specific on-resistance value of the VDMOS is reduced by 22% of that of the traditional VDMOS structure as the breakdown voltage maintained the same value in theory, and there is only one additional mask in processing the new structure VDMOS, which is easily fabricated. With the TCAD tool, one 200 V N-channel VDMOS with the new structure is analyzed, and simulated results show that a specific on-resistance value will reduce by 23%, and the value by 33% will be realized when the device is fabricated in three epitaxies and four buried layers. The novel structure can be widely used in the strip-gate VDMOS area.

关键词： VDMOS, on-resistance specific on-resistance breakdown voltage epitaxial layer resistance