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A novel switched capacitor bandgap reference with a correlated double sampling structure

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Journal of Semiconductors 2013年第2期34卷 109-112页

作者：陈建广郝跃国程玉华 System-on-Chip Laboratory Institute of MicroelectronicsPeking University Shanghai Research Institute of Microelectronics(Shrime) Peking University

A switched capacitor bandgap voltage reference with correlated double sampling structure embedded in a temperature sensor is implemented in a standard 0.35 um CMOS process. Due to the smaller change of the op-amp＇s output voltage, this topology is very suitable for low power applications. In addition, errors caused by the finite op-amp gain, input offset voltage, and 1/f noise are eliminated with the correlated double sampling technique. Additionally, two-level process calibration techniques are designed to minimize the process spread. Finally, a method of getting a full period valid reference voltage output is discussed and experimental results are provided to verify the effectiveness of the proposed structure.

关键词： bandgap correlated double sampling low power switched capacitor

Generalized switched-capacitor Step-up Multilevel Inverter Employing Single DC Source

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CSEE Journal of Power and Energy Systems 2022年第2期8卷 439-451页

作者： Yaoqiang Wang Kaige Wang Gen Li Fengjiang Wu Kewen Wang Jun Liang the School of Electrical Engineering Zhengzhou UniversityZhengzhou 450001China the Henan Engineering Research Center of Power Electronics and Energy Systems Zhengzhou 450001China Zhengzhou University Zhengzhou 450001China Zhoukou Power Supply Company State Grid Henan Electric Power Co.Ltd.Zhoukou 466000China Cardiff University Cardiff CF243AAU.K the Department of Electrical Engineering Harbin Institute of TechnologyHarbin 150001China

In this paper,a new generalized step-up multilevel DC-AC converter is proposed,which is suitable for applications with low-voltage input sources,such as photovoltaic power generation and electric *** inverter can achieve a high voltage gain by controlling the series-parallel conversion of the DC power supply and *** one DC voltage source and a few power devices are *** maximum output voltage and the number of output levels can be further increased through the switched-capacitor unit’s extension and the submodule cascaded ***,the capacitor voltages are self-balanced without complicated voltage control *** complementary operating mechanism between each pair of switches simplifies the modulation *** inductiveload ability is fully taken into account in the proposed ***,a remarkable characteristic of the inverter is that the charging and discharging states among different capacitors are synchronous,which reduces the voltage ripple of the frontend *** circuit structure,the working principle,the modulation strategy,the capacitors and losses analysis are presented in ***,the advantages of the proposed inverter are analyzed by comparing with other recently proposed ***,the steady-state and dynamic performance of the proposed inverter is verified and validated by simulation and experiment.

关键词： Modulation strategy multilevel inverter single DC source switched capacitor voltage self-balancing

A multifunctional switched-capacitor programmable gain amplifier for high-definition video analog front-ends

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Journal of Semiconductors 2015年第3期36卷 99-105页

作者：张鸿张杰张牡丹李雪程军 Department of Microelectronics Xi'an Jiaotong University Beijing Microelectronics Tech. Institution (BMTI)

A multifunctional programmable gain amplifier（PGA） that provides gain and offset adjusting abilities for high-definition video analog front-ends（AFE） is presented. With a switched-capacitor structure, the PGA also acts as a sample and holder of the analog-to-digital converter（ADC） in the AFE to reduce the power consumption and chip area of the whole AFE. Furthermore, the PGA converts the single-ended video signal into differential signal for the following ADC to reject common-mode noise and interferences. The 9-bit digital-to-analog converter（DAC） for gain and offset adjusting is embedded into the switched capacitor networks of the PGA. A video AFE integrated circuit based on the proposed PGA is fabricated in a 0.18- m process. Simulation and measurement results show that the PGA achieves a gain control range of 0.90 to 2.34 and an offset control range of –220 to220 mV while consuming 10.1 mA from a 1.8 V power supply.

关键词： PGA switched capacitor AFE offset adjustment embedded DAC

Genetic Algorithm Based 7-Level Step-Up Inverter with Reduced Harmonics and Switching Devices

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Intelligent Automation & Soft Computing 2023年第3期35卷 3081-3097页

作者： T.Anand Kumar M.Kaliamoorthy I.Gerald Christopher Raj Department of EEE Dr.Mahalingam College of Engineering and TechnologyPollachiTamilnaduIndia Department of EEE PSNA College of Engineering and TechnologyDindigulTamilnaduIndia

This paper presents a unique voltage-raising topology for a single-phase seven-level inverter with triple output voltage gain using single input source and two switched *** output voltage has been boosted up to three times the value of input voltage by conﬁguring the switched capacitors in series and parallel combinations which eliminates the use of additional step-up converters and *** selective harmonic elimination(SHE)approach is used to remove the lower-order *** optimal switching angles for SHE is determined using the genetic *** switching angles are com-bined with a level-shifted pulse width modulation(PWM)technique for pulse generation,resulting in reduced total harmonic distortion(THD).A detailed com-parison has been made against other relevant seven-level inverter topologies in terms of the number of switches,drivers,diodes,capacitors,and boosting facil-ities to emphasize the beneﬁts of the proposed *** proposed topology is simulated using MATLAB/SIMULINK and an experimental prototype has been developed to validate the *** Digital Signal Processing(DSP)TMS320F2812 board is used to generate the switching pulses for the proposed technique and the experimental results concur with the simulated model outputs.

关键词： Genetic algorithm multilevel inverter pulse width modulation selective harmonic elimination switched capacitor

A 16-bit cascaded sigma-delta pipeline A/D converter

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Journal of Semiconductors 2009年第5期30卷 103-108页

作者：李梁李儒章俞宙张加斌张俊安 National Key Laboratory of Analog ICs The 24th InstituteChina Electronics Technology Group Corporation

A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter （ADC） with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate. The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35μm CMOS process and achieves an SNR of 82 dB.

关键词： multi-bit sigma-delta ADC oversampling pipeline digital filter switched capacitor

High resolution interface circuit for closed-loop accelerometer

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Journal of Semiconductors 2011年第4期32卷 116-123页

作者：尹亮刘晓为陈伟平周治平 Department of Microelectronics Harbin Institute of Technology Key Laboratory of Micro-Systems and Micro-Structures Manufacturing Ministry of Education Department of Microelectronics Harbin Institute of TechnologyHarbin 150001China

This paper reports a low noise switched-capacitor CMOS interface circuit for the closed-loop operation of a capacitive *** time division multiplexing of the same electrode is adopted to avoid the strong feedthrough between capacitance sensing and electrostatic force feedback.A PID controller is designed to ensure the stability and dynamic response of a high Q closed-loop accelerometer with a vacuum *** architecture only requires single ended operational amplifiers,transmission gates and *** results show that a full scale acceleration of±3 g,non-linearity of 0.05%and signal bandwidth of 1000 Hz are *** complete module operates from a±5 V supply and has a measured sensitivity of 1.2 V/g with a noise of floor of 0.8μg/（Hz）;in *** chip is fabricated in the 2μm two-metal and two-poly n-well CMOS process with an area of 15.2 mm;.These results prove that this circuit is suitable for high performance micro-accelerometer applications like seismic detection and oil exploration.

关键词： closed-loop accelerometer interface circuit switched capacitor low noise

Compact DC-DC Converter for Pocket Micro-Controller Systems

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Journal of Computer Science & Technology 1996年第6期11卷 607-614页

作者：刘健陈治明钟彦儒杜忠 Xi'an Univ of Technology Xi'an China

Novel compact DC-DC converters for pocket micro-controller systems are discussed in the paper, which are based on switched capacitors and inductorless,consequently are more suitable for being hybridized. The new converters en-able the pocket microcontroller system to be powered by only one +12V source,while +5V and -12V are converted from the +12V source. The basic princi-ple, voltage ratio, efficiency and ripples are analysed. Experiment and SPICE simulation are also given, which show positive results.

关键词： DC-DC converter switched capacitor micro-controler system

A fourth-order bandwidth-reconfigurable delta-sigma modulator for audio applications

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Journal of Semiconductors 2012年第7期33卷 74-79页

作者：王俊乾杨海峰魏蕊许俊任俊彦 State Key Laboratory of ASIC&System Fudan University Microelectronics Science and Technology Innovation Platform Fudan University

A single loop fourth-order delta-sigma modulator is presented for audio applications. A reconfigurable mechanism is adopted for two bandwidth-based modes （8 kHz/16 kHz）. Manufactured in the SM1C 0.13μm CMOS mixed signal process, the chip consumes low power （153.6 μW） and occupies a core area of 0.98×0.46 mm2. The presented modulator achieves an 89.3 dB SNR and 90.2 dB dynamic range in 16 kHz mode, as well as a 90.2 dB SNR and 86 dB dynamic range in 8 kHz mode. The designed modulator shows a very competitive figure of merit among state-of-the-art low voltage modulators.

关键词： delta-sigma modulator feedforward architecture reconfiguration switched capacitor bootstrappedswitch

Design of a high-order single-loop Σ△ ADC followed by a decimator in 0.18μm CMOS technology

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Journal of Semiconductors 2009年第10期30卷 94-99页

作者：李迪杨银堂石立春吴笑峰 School of Microelectronics Xidian University

This work presents an oversampled high-order single-loop single-bit sigma–delta analog-to-digital converter followed by a multi-stage decimation *** details and measurement results for the whole chip are presented for a TSMC 0.18μm CMOS implementation to achieve virtually ideal 16-b performance over a baseband of 640 *** modulator in this work is a fully differential circuit that operates from a single 1.8 V power supply. With an oversampling ratio of 64 and a clock rate of 81.92 MHz,the modulator achieves a 94 dB dynamic range. The decimator achieves a pass-band ripple of less than 0.01 dB,a stop-band attenuation of 80 dB and a transition band from 640 to 740 *** whole chip consumes only 56 mW for a 1.28 MHz output rate and occupies a die area of 1×2 mm^2.

关键词： oversampled analog-to-digital converter sigma-delta modulator decimator switched capacitor