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An Improved Polar Codes-Based Key Reconciliation for Practical Quantum Key Distribution

Chinese Journal of Electronics 2018年第2期27卷 250-255页

作者： YAN Shiling WANG Jindong FANG Junbin JIANG Lin WANG Xuan Laboratory of Quantum Engineering and Quantum Materials South China Normal University Department of Optoelectronic Engineering Jinan University The Edward S.Rogers Sr.Department of Electrical & Computer Engineering University of Toronto Harbin Institute of Technology Shenzhen Graduate School

Key reconciliation is important for practical Quantum key distribution（QKD） systems since it corrects the error bits in a key string by sacrificing some key bits. Therefore, its performance directly affects the secret key rate of a practical QKD system. Although key reconciliation scheme based on polar codes can achieve a high coding efficiency, the high frame error rate causes discarding key strings and decreases the secret key rate. In this paper, we fist analyze the limitation of successive cancellation decoding of polar codes, and then we propose an improved key reconciliation scheme using polar codes with successive cancellation list decoding and optimized coding structures, which can decrease the frame error probability, resulting in a higher secret key rate. Numerical results show that the proposed scheme can achieve a 12.8% higher secret key rate than the previous polar codes-based scheme with a code length of 216 bits and a quantum bit error rate of 2%. Besides, the proposed scheme is robust and it can extract secret key bits even when the quantum bit error rate reaches 10.2% with a code length of 2;bits and a coding efficiency of 90.6%.

关键词： Quantum key distribution Polar codes successive cancellation list decoding Secret key rate

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Partial CRC-aided decoding of 5G-NR short codes using reliability information

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Science China(Information Sciences) 2019年第8期62卷 35-43页

作者： Ming JIANG Zhengyi LI Xiao YANG Chunming ZHAO National Mobile Communications Research Laboratory Southeast University

In this paper, we focus on how to further enhance the performance of the channel codes in order to meet the more stringent reliability requirements of future networks(5G and beyond). A general decoder with the aid of partial cyclic redundancy check(CRC) bits is proposed for the polar codes and short low-density parity-check(LDPC) codes in 5G systems. The decoder based on ordered statistic decoding(OSD) method can effectively improve the error-correction performance on the condition that extra CRC bits are used to assist in decoding. Meanwhile, the remaining part of CRC keeps its capability of errordetection to guarantee the undetected error rate low enough. This paper gives the detailed implementation schemes of the partial CRC-aided OSD process and its combination with the conventional decodings of the LDPC/polar codes in 5G systems. The simulation results show our proposed decoding scheme achieves a promising trade-off between the performance gain and the error-detection capabilities.

关键词： polar codes LDPC codes CRC codes successive cancellation list decoding ordered statistic decoding

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Deep Learning Aided SCL decoding of Polar Codes with Shifted-Pruning

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China Communications 2023年第1期20卷 153-170页

作者： Yang Lu Mingmin Zhao Ming Lei Chan Wang Minjian Zhao College of Information Science and Electronic Engineering Zhejiang UniversityHangzhou 310027China Zhejiang Provincial Key Laboratory of Information Processing Communication and Networking(IPCAN)Hangzhou 310027China

Recently,a generalized successive cancellation list(SCL)decoder implemented with shiftedpruning(SP)scheme,namely the SCL-SP-ωdecoder,is presented for polar codes,which is able to shift the pruning window at mostωtimes during each SCL re-decoding attempt to prevent the correct path from being *** candidate positions for applying the SP scheme are selected by a shifting metric based on the probability that the elimination ***,the number of exponential/logarithm operations involved in the SCL-SP-ωdecoder grows linearly with the number of information bits and list size,which leads to high computational *** this paper,we present a detailed analysis of the SCL-SP-ωdecoder in terms of the decoding performance and complexity,which unveils that the choice of the shifting metric is essential for improving the decoding performance and reducing the re-decoding attempts ***,we introduce a simplified metric derived from the path metric(PM)domain,and a custom-tailored deep learning(DL)network is further designed to enhance the efficiency of the proposed simplified *** proposed metrics are both free of transcendental functions and hence,are more hardware-friendly than the existing *** results show that the proposed DL-aided metric provides the best error correction performance as comparison with the state of the art.

关键词： polar codes successive cancellation list decoding deep learning shifted-pruning path metric

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list-Serial Pipelined Hardware Architecture for SCL decoding of Polar Codes

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China Communications 2023年第3期20卷 175-184页

作者： Zhongxiu Feng Cong Niu Zhengyu Zhang Jiaxi Zhou Daiming Qu Tao Jiang Research Center of 6G Mobile Communications School of Cyber Science and Engineeringand Wuhan National Laboratory for OptoelectronicsHuazhong University of Science and TechnologyWuhan 430074China Institute of Space Integrated Ground Network Hefei 230094China The 38th Research Institute of China Electronics Technology Group Corporation Hefei 230088China School of Electronics Information and Communications Huazhong University of Science and TechnologyWuhan 430074China

For polar codes,the performance of successive cancellation list(SCL)decoding is capable of approaching that of maximum likelihood ***,the existing hardware architectures for the SCL decoding suffer from high hardware complexity due to calculating L decoding paths simultaneously,which are unfriendly to the devices with limited logical resources,such as field programmable gate arrays(FPGAs).In this paper,we propose a list-serial pipelined hardware architecture with low complexity for the SCL decoding,where the serial calculation and the pipelined operation are elegantly combined to strike a balance between the complexity and the ***,we employ only one successive cancellation(SC)decoder core without L×L crossbars,and reduce the number of inputs of the metric sorter from 2L to L+***,the FPGA implementations show that the hardware resource consumption is significantly reduced with negligible decoding performance loss.

关键词： successive cancellation list decoding po-lar codes hardware implementation pipelined archi-tecture

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