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A low-power CMOS smart temperature sensor for RFID application

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Journal of Semiconductors 2014年第11期35卷 107-113页

作者：谢良波刘佳欣王耀文光俊 Centre for RFIC and System Technology School of Communication and Information EngineeringUniversity of Electronic Science and Technology of China

This paper presents the design and implement ofa CMOS smart temperature sensor, which consists of a low power analog front-end and a 12-bit low-power successive approximation register （SAR） analog-to-digital converter （ADC）. The analog front-end generates a proportional-to-absolute-temperature （PTAT） voltage with MOS- FET circuits operating in the sub-threshold region. A reference voltage is also generated and optimized in order to minimize the temperature error and the 12-bit SAR ADC is used to digitize the PTAT voltage. Using 0.18 μm CMOS technology, measurement results show that the temperature error is -0.69/＋0.85 ℃ after one-point calibra- tion over a temperature range of-40 to 100 ℃. Under a conversion speed of 1K samples/s, the power consumption is only 2.02 μW while the chip area is 230 × 225 μm2, and it is suitable for RFID application.

关键词： CMOS low power temperature sensor sub-threshold SAR ADC

Leakage Reduction Using DTSCL and Current Mirror SCL Logic Structures for LP-LV Circuits

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Circuits and Systems 2013年第1期4卷 20-28页

作者： Sanjeev Rai Ram Awadh Mishra Sudarshan Tiwari Department of Electronics & Communication Engineering M.N.N.I.T Allahabad India National Institute of Technology Raipur India

This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the performance of these structures with STSCL (sub-threshold SCL). The first design under consideration is DTPMOS as load device which analyses the performance of Dynamic threshold SCL (DTSCL) Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power-delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design under consideration uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic (CMSCL) can be used for high speed operation. The advantage of this design is that it provides 54% reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control over power dissipation. Measurements of test structures simulated in 0.18 μm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits. Cadence Virtuoso schematic editor and Spectre Simulation tools have been used.

关键词： CMOS Integrated Circuits CMOS Logic Circuit Dynamic threshold MOS (DTMOS) Power-Delay Product Source-Coupled Logic (SCL) sub-threshold CMOS sub-threshold SCL Ultra-Low-Power Circuits Weak Inversion LP-LV(Low Power-Low Voltage)

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

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Circuits and Systems 2017年第2期8卷 23-52页

作者： Pavankumar Bikki Pitchai Karuppanan Department of Electronics and Communication Motilal Nehru National Institute of Technology Allahabad India

Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during the data holding operation, the stored memory data are more affected by the leakage phenomena in the circuit while the device parameters are scaled down. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. A classification of these approaches made based on their key design and functions, such as biasing technique, power gating and multi-threshold techniques. Based on our survey, we summarize the merits and demerits and challenges of these techniques. This comprehensive study will be helpful to extend the further research for future implementations.

关键词： Body Biasing Gate Leakage Junction Leakage Power Gating Multi-threshold SRAM Cell sub-threshold Leakage

Characterization of a Novel Low-Power SRAM Bit-Cell Structure at Deep sub-Micron CMOS Technology for Multimedia Applications

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Circuits and Systems 2012年第1期3卷 23-28页

作者： Rakesh Kumar Singh Manisha Pattanaik Neeraj Kr. Shukla Department of E & CE BT-Kumaon Engineering College Department of Information Technology VLSI Group ABV-IIITM Gwalior Department of EECE ITM University

To meet the increasing demands for higher performance and low-power consumption in present and future Systems-on-Chips (SoCs) require a large amount of on-die/embedded memory. In Deep-sub-Micron (DSM) technology, it is coming as challenges, e.g., leakage power, performance, data retentation, and stability issues. In this work, we have proposed a novel low-stress SRAM cell, called as IP3 SRAM bit-cell, as an integrated cell. It has a separate write sub-cell and read sub-cell, where the write sub-cell has dual role of data write and data hold. The data read sub-cell is proposed as a pMOS gated ground scheme to further reduce the read power by lowering the gate and subthreshold leakage currents. The drowsy voltage is applied to the cell when the memory is in the standby mode. Further, it utilizes the full-supply body biasing scheme while the memory is in the standby mode, to further reduce the subthreshold leakage current to reduce the overall standby power. To the best of our knowledge, this low-stress memory cell has been proposed for the first time. The proposed IP3 SRAM Cell has a significant write and read power reduction as compared to the conventional 6 T and PP SRAM cells and overall improved read stability and write ability performances. The proposed design is being simulated at VDD = 0.8 V and 0.7 V and an analysis is presented here for 0.8 V to adhere previously reported works. The other design parameters are taken from the CMOS technology available on 45 nm with tOX = 2.4 nm, Vthn = 0.224 V, and Vthp = 0.24 V at T = 27?C.

关键词： SRAM Low-Power Active Power Standby Power Gate Leakage sub-threshold Leakage

A Super Low Power CMOS Receiver for High Resolution Epi-retinal Prosthesis

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Journal of Energy and Power Engineering 2010年第8期4卷 32-39页

作者： J.W. Yang N. Tran S. Bai D.C. Ng M. Halpern E. Skafidas Department of Electrical and Electronic Engineering The University of Melbourne Parkville I＇ictoria 3010 Australia

The authors report a super low power Medical Implant Communication Service （MICS） band receiver for a high resolution epi-retinal prosthesis （BionicEye）. The frequency shift keying （FSK） receiver consumes less than 1.5 mW power with 1 V supply. It is able to achieve a maximum data rate of 400 kb/s. This paper presents the research work carried out on designing a fully-integrated sub-threshold receiver fabricated on a 65 nm complimentary metal oxide semiconductor （CMOS） chip. In order to achieve super low power consumption, more than 90% of the transistors in all analog building blocks are operated in sub-threshold region. System level issues, such as required receiver architecture and specifications are also addressed.

关键词： Super low power fully-integrated sub-threshold MICS band. BionicEye.

Analysis of 8T SRAM Cell at Various Process Corners at 65 nm Process Technology

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Circuits and Systems 2011年第4期2卷 326-329页

作者： Shilpi Birla Neeraj Kumar Shukla Kapil Rathi Rakesh Kumar Singh Manisha Pattanaik Department of Electronics & Communications Sir Padampat Singhania University Department of ECE ITM University Texas Instruments

In Present scenario battery-powered hand-held multimedia systems become popular. The power consumption in these devices is a major concern these days for its long operational life. Although various techniques to reduce the power dissipation has been developed. The most adopted method is to lower the supply voltage. But lowering the Vdd reduces the gate current much more rapidly than the sub-threshold current and degrades the SNM. This degraded SNM further limits the voltage scaling. To improve the stability of the SRAM cell topology of the conventional 6T Static Random Access Memory (SRAM) cell has been changed and revised to 8T and 10T cell, the topologies. This work has analyzed the SRAM’s Static Noise Margin (SNM) at 8T for various process corners at 65nm technology. It evaluates the SNM along with the write margins of the cell along with the cell size of 8T SRAM bit-cell operating in sub-threshold voltage at various process corners. It is observed that an 8T cell has 13 % better write margin than conventional 6T SRAM cell. This paper analyses the dependence of SNM of SRAM memory cell on supply voltage, temperature, transistor sizing in 65nm technology at various process corners (TT, SS, FF, FS, and SF).

关键词： SNM sub-threshold Current Gate Current Process Corners