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Measurement of residual stress in a multi-layer semiconductor heterostructure by micro-Raman spectroscopy

Acta Mechanica Sinica 2016年第5期32卷 805-812页

作者： Wei Qiu Cui-Li Cheng Ren-Rong Liang Chun-Wang Zhao Zhen-Kun Lei Yu-Cheng Zhao Lu-Lu Ma Jun Xu Hua-Jun Fang Yi-Lan Kang Tianjin Key Laboratory of Modern Engineering Mechanics Department of Mechanics Tianjin UniversityTianjin 300072China Institute of Microelectronics Tsinghua UniversityBeijing 100084China College of Art and Sciences Shanghai Maritime UniversityShanghai 201306China State Key Laboratory of Structural Analysis for Industrial Equipment Dalian University of TechnologyDalian 116024China Graduate School of the Chinese Academy of Sciences Beijing 100049China

Si-based multilayer structures are widely used in current microelectronics. During their preparation, some inhomogeneous residual stress is induced, resulting in competition between interface mismatching and surface energy and even leading to structure failure. This work presents a methodological study on the measurement of residual stress in a multi-layer semiconductor heterostructure. Scanning electron microscopy（SEM）, micro-Raman spectroscopy（MRS）, and transmission electron microscopy（TEM） were applied to measure the geometric parameters of the multilayer structure. The relationship between the Raman spectrum and the stress/strain on the [100] and [110] crystal orientations was determined to enable surface and crosssection residual stress analyses, respectively. Based on the Raman mapping results, the distribution of residual stress along the depth of the multi-layer heterostructure was successfully obtained.

关键词： Residual stress Multi-layer semiconductor heterostructure Micro-Raman spectroscopy(MRS) strained silicon Germanium silicon

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Growth of strained-Si material using low-temperature Si combined with ion implantation technology

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Journal of Semiconductors 2010年第6期31卷 12-15页

作者：杨洪东于奇王向展李竞春宁宁杨谟华 State Key Laboratory of Electronic Thin Films and Integrated Devices University of Electronic Science and Technology

In order to fabricate strained-Si MOSFETs,we present a method to prepare strained-Si material with highquality surface and ultra-thin SiGe virtual *** sandwiching a low-temperature Si（LT-Si） layer between a Si buffer and a pseudomorphic Si_（0.8）Ge_（0.2） layer,the surface roughness root mean square（RMS） is 1.02 nm and the defect density is 10~6 cm^（-2） owing to the misfit dislocations restricted to the LT-Si layer and the threading dislocations suppressed from penetrating into the Si_（0.8）Ge_（0.2） *** employing P~＋ implantation and rapid thermal annealing, the strain relaxation degree of the Si_（0.8）Ge_（0.2） layer increases from 85.09%to 96.41%and relaxation is more uniform. Meanwhile,the RMS（1.1nm） varies a little and the defect density varies *** to the results,the method of combining an LT-Si layer with ion implantation can prepare high-quality strained-Si material with a high relaxation degree and ultra-thin SiGe virtual substrate to meet the requirements of device applications.

关键词： low-temperature silicon strained silicon ion implantation SiGe virtual substrate

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Advanced strain engineering for state-of-the-artnanoscale CMOS technology

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Science China(Information Sciences) 2011年第5期54卷 946-958页

作者： YANG Bin (Frank)1 & CAI Ming2 1Globalfoundries, 2070 Rt. 52, Hopewell Junction, NY 12533, USA 2IBM Semiconductor Research & Development Center, 2070 Rt. 52, Hopewell Junction, NY 12533, USA Globalfoundries New York USA IBM Semiconductor Research & Development Center New York USA

The introduction and advancement of strain engineering has been one of the most critical features for the state-of-the-art nanoscale CMOS transistors. This paper provides an overview of the major strain engineering techniques that have remarkably re-shaped the advanced CMOS transistor architecture, including embedded SiGe (eSiGe), embedded Si:C (eSi:C), stress memorization technique (SMT), dual stress liners (DSL), and stress proximity technique (SPT). The advent of high-K/metal-gate (HKMG) also brings in additional strain benefit with its metal gate stressor (MGS) and replacement gate (RMG) process. Strain engineering continues to evolve and will remain to be one of the key performance enablers for the future generation of CMOS technologies.

关键词： strained silicon embedded SiGe embedded Si:C stress memorization technique dual stress liners high-K/metal-gate

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