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Partial-TMR: A New Method for Protecting Register Files Against soft error Based on Lifetime Analysis

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Journal of Computer Science & Technology 2021年第5期36卷 1089-1101页

作者： Xian-Geng Liang Ying-Ke Gao Geng-Xin Hua Beijing Institute of Control Engineering China Academy of Space TechnologyBeijing 100090China

High-energy particles in the space can easily cause soft error in register file(RF).As a critical structure in a processor,RF often stores data for long periods of time and is read frequently,resulting in a higher probability of spreading corrupted data to other parts of the *** triple modular redundancy(TMR)is a common and effective fault tolerance method that enables multi-bit error *** full TMR for all the registers could cause excessive area and power ***,some registers in RF have less impact on processor ***,there is no need to design TMR for *** paper designs an efficient strategy which can rate the registers in RF based on their *** on the proposed strategy,a new RF fault tolerance method named Partial-TMR formulates in this paper,which selectively protects more vulnerable registers against multi-bit error,and improves fault tolerance *** integer RF,Partial-TMR improves its soft error correction capability by 24.5%relative to the baseline system and 3%relative to ParShield,while for floating-point RF,the improvement comes to 5.17%and 0.58%*** soft error correction capability of Partial-TMR is slightly lower than that of full TMR by 1%to 3%,but Partial-TMR significantly cuts the area and power *** with full TMR,Partial-TMR decreases the area and power overheads by 71.6%and 64.9%,*** also has little impact on the ***-TMR is a more cost-effective fault tolerance method compared with ParShield and full TMR.

关键词： register file soft error lifetime analysis selective protection triple modular redundancy(TMR)

SS-SERA:An improved framework for architectural level soft error reliability analysis

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Journal of Central South University 2012年第11期19卷 3129-3146页

作者：成玉马安国王永文唐遇星张民选 School of Computer Science National University of Defense Technology People's Liberation Army Troops 61741

Integrated with an improved architectural vulnerability factor （AVF） computing model, a new architectural level soft error reliability analysis framework, SS-SERA （soft error reliability analysis based on SimpleScalar）, was developed. SS-SERA was used to estimate the AVFs for various on-chip structures accurately. Experimental results show that the AVFs of issue queue （IQ）, register update units （RUU）, load store queue （LSQ） and functional unit （FU） are 38.11%, 22.17%, 23.05% and 24.43%, respectively. For address-based structures, i.e., levell data cache （LID）, DTLB, level2 unified cache （L2U）, levell instruction cache （LII） and ITLB, AVFs of their data arrays are 22.86%, 27.57%, 14.80%, 8.25% and 12.58%, lower than their tag arrays＇ AVFs which are 30.01%, 28.89%, 17.69%, 10.26% and 13.84%, respectively. Furthermore, using the AVF values obtained with SS-SERA, a qualitative and quantitative analysis of the AVF variation and predictability was performed for the structures studied. Experimental results show that the AVF exhibits significant variations across different structures and workloads, and is influenced by multiple microarchitectural metrics and their interactions. Besides, AVFs of SPEC2K floating point programs exhibit better predictability than SPEC2K integer programs.

关键词： soft error architectural vulnerability factor (AVF) AVF estimation model

Prevention from soft errors via Architecture Elasticity

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Journal of Computer Science & Technology 2014年第2期29卷 247-254页

作者：尹一笑陈云霁郭崎陈天石 State Key Lab of Computer Architecture and Microprocessor Research Center Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences Loongson Technology Corporation Limited IBM Research-China

Due to the decreasing threshold voltages, shrinking feature size, as well as the exponential growth of on-chip transistors, modern processors are increasingly vulnerable to soft errors. However, traditional mechanisms of soft error mitigation take actions to deal with soft errors only after they have been detected. Instead of the passive responses, this paper proposes a novel mechanism which proactively prevents from the occurrence of soft errors via architecture elasticity. In the light of a predictive model, we adapt the processor architectures h01istically and dynamically. The predictive model provides the ability to quickly and accurately predict the simulation target across different program execution phases on any architecture configurations by leveraging an artificial neural network model. Experimental results on SPEC CPU 2000 benchmarks show that our method inherently reduces the soft error rate by 33.2% and improves the energy efficiency by 18.3% as compared with the static configuration processor.

关键词： soft error energy efficiency architecture elasticity

Reducing vulnerability to soft errors in sub-100 nm content addressable memory circuits

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Journal of Semiconductors 2010年第2期31卷 94-98页

作者：孙岩张甲兴张民选郝跃 School of Computer National University of Defense Technology School of Microelectronics Xidian University

We first study the impacts of soft errors on various types of CAM for different feature *** presenting a soft error immune CAM cell,SSB-RCAM,we propose two kinds of reliable CAM,DCF-RCAM and DCK-RCAM. In addition,we present an ignore mechanism to protect dual cell redundancy CAMs against soft *** results indicate that the 11T-NOR CAM cell has an advantage in soft error *** on 11T-NOR,the proposed reliable CAMs reduce the SER by about 81%on average with acceptable *** SER of dual cell redundancy CAMs can also be decreased using the ignore mechanism in specific applications.

关键词： soft error content addressable memory reliability vulnerability critical charge

A novel radiation hardened by design latch

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Journal of Semiconductors 2009年第3期30卷 118-121页

作者：黄正峰梁华国 School of Computer and Information Hefei University of Technology

Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-eventupset （SEU） immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the presented latch are evaluated by detailed SPICE simulations. Compared with previous SEU-hardening solutions such as TMR-Latch, the presented latch is more area efficient, delay and power efficient. Fault injection simulations also demonstrate the robustness of the presented latch even under high energy particle strikes.

关键词： soft error single event upset radiation hardened by design latch

Design of Novel and Low Cost Triple-node Upset Self-recoverable Latch

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原子能科学技术 2023年第12期57卷 2326-2336页

作者： BAI Na MING Tianbo XU Yaohua WANG Yi LI Yunfei LI Li Information Materials and Intelligent Sensing Laboratory of Anhui Province Anhui UniversityHefei 230601China Shanxi Key Laboratory of Advanced Semiconductor Optoelectronic Devices and Integrated Systems Jincheng 048000China Jincheng Research Institute of Opo-mechatronics Industry Jincheng 048000China

With the development of semiconductor technology,the size of transistors continues to *** complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Currently,single-node upset(SNU),double-node upset(DNU)and triple-node upset(TNU)caused by SE are relatively ***’s solution is not yet fully mature.A novel and low-cost TNU self-recoverable latch(named NLCTNURL)was designed which is resistant to harsh radiation *** analyzing circuit resiliency,a double-exponential current source is used to simulate the flipping behavior of a node’s stored value when an error *** results show that the latch has full TNU self-recovery.A comparative analysis was conducted on seven latches related to ***,a comprehensive index combining delay,power,area and self-recovery—DPAN index was proposed,and all eight types of latches from the perspectives of delay,power,area,and DPAN index were analyzed and *** simulation results show that compared with the latches LCTNURL and TNURL which can also achieve TNU self-recoverable,NLCTNURL is reduced by 68.23%and 57.46%respectively from the perspective of *** the perspective of power,NLCTNURL is reduced by 72.84%and 74.19%,*** the area perspective,NLCTNURL is reduced by about 28.57%and 53.13%,*** the DPAN index perspective,NLCTNURL is reduced by about 93.12%and 97.31%.The simulation results show that the delay and power stability of the circuit are very high no matter in different temperatures or operating voltages.

关键词： circuit reliability latch design self-recoverability soft error radiation hardening triple-node upset

Multi-objective Particle Swarm Optimization Algorithm Based on Performance and Reliability of Discrete System Resources Configuration

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Journal of Donghua University(English Edition) 2014年第6期31卷 850-852页

作者：周国财高翔 School of Astronautics Northwestern Polytechnical University China Academy of Space Technology

Considering research on multi-objective optimization for reliability and performance suffering cost constraints in digital circuits,an improved multi-objective optimization algorithm based on performance and reliability was proposed to solve the problem of discrete system resources configuration in this paper. This algorithm used the particle-swarm optimization( PSO) to evaluate the tradeoffs configuration of the system resources between reliability and performance and proved the feasibility through the ***, the information of resources configuration from optimization algorithm was used to effectively guide the system design so as to mitigate soft errors caused by single event effect( SEE).

关键词： multi-objective optimization function module soft error triple modular redundancy(TMR)

Implementation and Analysis of Probabilistic Methods for Gate-Level Circuit Reliability Estimation

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Tsinghua Science and Technology 2007年第S1期12卷 32-38页

作者：王真江建慧杨光 Key Laboratory of Embedded Systems and Service Computing Ministry of Education of Shanghai Department of Computer Science and Technology Tongji University

The development of VLSI technology results in the dramatically improvement of the performance of integrated circuits. However, it brings more challenges to the aspect of reliability. Integrated circuits become more susceptible to soft errors. Therefore, it is imperative to study the reliability of circuits under the soft error. This paper implements three probabilistic methods (two pass, error propagation probability, and probabilistic transfer matrix) for estimating gate-level circuit reliability on PC. The functions and performance of these methods are compared by experiments using ISCAS85 and 74-series circuits.

关键词： soft error soft error rate signal reliability failure probability reliability estimation

A novel double-node-upset-resilient radiation-hardened latch

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Journal of Southeast University(English Edition) 2018年第2期34卷 182-186页

作者： Wang Qijun Yan Aibin School of Computer Science and Technology Anhui UniversityHefei 230601China

To effectively tolerate a double-node upset,a novel double-node-upset-resilient radiation-hardened latch is proposed in 22 nm complementary-metal-oxide-semiconductor *** three interlocked single-node-upset-resilient cells,which are identically mainly constructed from three mutually feeding back 2-input C-elements,the latch achieves *** smaller transistor sizes,clock-gating technology,and high-speed transmission-path,the cost of the latch is effectively *** results demonstrate the double-node-upset-resilience of the latch and also show that compared with the up-to-date double-node-upset-resilient latches,the proposed latch reduces the transmission delay by 72.54%,the power dissipation by 33.97%,and the delay-power-area product by 78.57%,while the average cost of the silicon area is only increased by 16.45%.

关键词： radiation hardening circuit reliability soft error double-node upset single-node upset