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Science China(Information Sciences) 2018年第11期61卷 31-47页

作者： Xiaowei LI Guihai YAN Jing YE Ying WANG State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences University of Chinese Academy of Sciences

If your computer crashes, you can revive it by a reboot, an empirical solution that usually turns out to be effective. The rationale behind this solution is that transient faults, either in hardware or software,can be fixed by refreshing the machine state. Such a "silver bullet", however, could be futile in the future because the faults, especially those existing in the hardware such as Integrated Circuit(IC) chips, cannot be eliminated by refreshing. What we need is a more sophisticated mechanism to steer the system back to the right track. The "magic cure" is the Fault Tolerance On-Chip(FTOC) mechanism, which relies on a suite of built-in design-for-reliability logic, including fault detection, fault diagnosis, and error recovery, working in a self-supportive manner. We have exploited the FTOC to build a holistic solution ranging from on-chip fault detection to error recovery mechanisms to address faults caused by chips progressively aging. Besides fault detection, the FTOC paradigm provides attractive benefits, such as facilitating graceful performance degradation, mitigating the impact of verification blind spots, and improving the chip yield.

关键词： fault tolerance on-chip self-test self-diagnosis self-repair

test Time Minimization for Hybrid BIST of Core-Based Systems

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Journal of Computer Science & Technology 2006年第6期21卷 907-912页

作者： Gert Jervan Petru Eles Zebo Peng Raimund Ubar Maksim Jenihhin Embedded Systems Laboratory (ESLAB) Linkoeing University Sweden Department of Computer Engineering Tallinn University of Technology Estonia

This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are generated online, and deterministic test patterns that are generated off-line and stored in the system. In this paper we propose an iterative algorithm to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach cmploys a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find near optimal solutions.

关键词： SoC self-test hybrid BIST

A Fully Differential Interface Circuit of Closed-loop Accelerometer with Force Feedback Linearization

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Journal of Harbin Institute of Technology(New Series) 2014年第3期21卷 18-23页

作者： Hong-Lin Xu Hong-Na Liu Chong He Liang Yin Xiao-Wei Liu Micro-Electromechanical System Center Harbin Institute of Technology Key Laboratory of Micro-Systems and Micro-Structures Manufacturing Ministry of Education

In this paper,a fifth-order fully differential interface circuit( IC) is presented to improve the noise performance for micromechanical sigma-delta( Σ-Δ) accelerometer. A lead compensator is adopted to ensure the stability of the closed-loop high-order system. A low noise capacitance detection circuit is described with a correlated-double-sampling( CDS) technique to decrease 1 /f noise and offset of the operational amplifier. This paper also proposes a self-test technique for the interface circuit to test the harmonic distortion. An electrostatic force feedback linearization circuit is presented to reduce the harmonic distortion resulting in larger dynamic range( DR). The layout of the IC is implemented in a standard 0. 6 μm CMOS technology and operates at a sampling frequency of 250 kHz. The interface consumes 20 mW from a 5 V supply. The post-simulation results indicate that the noise floor of the digital accelerometer is about- 140 dBV /Hz1 /2at low frequency. The sensitivity is 2. 5 V /g and the nonlinearity is 0. 11%. The self-test function is achieved with 98. 2 dB thirdorder harmonic distortion detection based on the electrostatic force feedback linearization.

关键词： sigma-delta accelerometer self-test harmonic distortion electrostatic force feedback linearization

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ON SHORTENING test SEQUENCE LENGTH FOR SIGNATURE ANALYZER

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Journal of Electronics(China) 1995年第2期12卷 151-159页

作者：丁瑾胡健栋 Beijing University of Posts and Telecommunications Beijing 100088

Based on the built-in self-test for logic circuit, a new approach is proposed to reduce pseudorandom test length. After finding worst faults in the circuit and creating their circuit models the output signals of these models will be compressed by linear feedback shift register. The test length for the worst faults can be obtained by analyzing compressed signature . Finally, using the relation between input probability and test length, we propose a new algorithm to shorten the test sequence length. So the optimum input probability and the shortest test length can be received.

关键词： Built-in self-test Worst fault Signature analysis Probability optimization

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A Review of the Calculation Formula for the Four-component Borehole Strainmeter and Application to Earthquake Cases

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Earthquake Research in China 2019年第1期33卷 132-146页

作者： SU Kaizhi Institute of Crustal Dynamics China Earthquake Administration

Based on the principle formula for the four-component strainmeters, we can directly obtain the specific plane strain, shear strain and azimuthal angle of the principal strain, and the maximum and minimum principal strains calculated afterwards are the indirect result. The problems of practicality of the sensitivity coefficients A and B of plane strain and shear strain are then discussed. Based on this idea, we analyzed the observation data of several four-component borehole strainmeters near the epicenter of the Yiliang M_S5.7 earthquake in 2012 and the Ludian M_S6.5 earthquake in 2014 in the Zhaotong area, Yunnan Province. The results show that the analysis based on the perspective of plane strain and shear strain has an obviously better effect than that based on the component readings, and can directly peel off the respective abnormality of the plane strain and shear strain. In addition, the correlation coefficient curves between measured data of two plane strains show significant anomalies which often occur several days before and during the earthquake.

关键词： Four-component borehole strainmeter Ludian MS6. 5 earthquake Yiliang MS5. 7 earthquake Plane strain abnormality Shear strain abnormality self-test of data Strain anomaly

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