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2010 3rd IEEE International Conference on Computer Science and Information Technology—ICCSIT 2010

作者： Benzhai Hai Dep.of Computer Science &Technology Henan Normal University Xinxiang China Ruiyun Xie Dep.of Computer Science &Technology Henan Mechanical and Electrical Engineering College Xinxiang China Fangfang Li Dep.Of Metallurgy Hunan University of Technology Zhuzhou China Yanhao Chen Network Center Henan Normal University Xinxiang China

In this paper a uniform calculus-based approach for synthesizing monitors checking correctness properties specified by a large variety of logics at runtime is provided, including future and past time logics, interval logics, state machine and parameterized temporal logics. Thus we can synthesize monitors from the logical specification in an uniform fashion to incrementally analysis the current execution traces during test and real run. The monitor detects both good and bad prefix of a particular kind, namely those that are informative for the property under investigation.

关键词： Calculus runtime verification synthesizing monitors

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TRAP:trace runtime analysis of properties

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Frontiers of Computer Science 2020年第3期14卷 15-29页

作者： Daian YUE Vania JOLOBOFF Frederic MALLET MOE Trustworthy Software International Joint Lab East China Normal UniversityShanghai 200062China INRIA Rennes 35042France Universite Cote d'Azur CNRSINRIAI3SSophia Antipolis 06900France

We present a method and a tool for the verification of causal and temporal properties for embedded systems.We analyze trace streams resulting from the execution of virtual prototypes that combine simulated hardware and embedded software.The main originality lies in the use of logical clocks to abstract away irrelevant information from the trace.We propose a model-based approach that relies on domain specific languages(DSL).A first DSL,called TISL(trace item specification language),captures the relevant data structures.A second DSL,called STML(simulation trace mapping language),abstracts the simulation raw data into logical clocks,abstracting simulation data into relevant observation probes and thus reducing the trace streams size.The third DSL,called TPSL,defines a set of behavioral patterns that include widely used temporal properties.This is meant for users who are not familiar with temporal logics.Each pattern is transformed into an automata.All the automata are executed concurrently and each one raises an error if and when the related TPSL property is violated.The contribution is the integration of this pattern-based property specification language into the SimSoC virtual prototyping framework without requiring to recompile all the simulation models when the properties evolve.We illustrate our approach with experiments that show the possibility to use multi-core platforms to parallelize the simulation and verification processes,thus reducing the verification time.

关键词： runtime verification trace analysis property specification logical clocks simulation virtual prototyping

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Anticipatory active monitoring for safety-and security-critical software

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Science China(Information Sciences) 2012年第12期55卷 2723-2737页

作者： Martin LEUCKER Institute of Software Technology and Programming Languages University of Lbeck

Since formal verification and testing of systems is normally faced with challenges such as state explosion and uncertain execution environments,it is extremely difficult to exhaustively verify and test software during the development phase.Therefore,monitoring has become an indispensable means for finding latent software faults at runtime.Most current monitoring approaches only generate passive monitors,which cannot foresee possible faults and consequently cannot prevent their occurrence.In this paper,we propose an active monitoring approach based on runtime verification.This approach aims to predict possible incoming violations using a monitor that executes anticipatory semantics of temporal logic,and then generates the necessary steering actions according to a partial system model,which steers the system away from paths causing these violations.In this case,the monitor and monitored system make up a discrete feedback control loop.We further investigate the control theory behind active monitoring so that non-blocking controllability can be achieved.The results of applying active monitoring to two cases,a railway crossing control system and security-enhanced Linux(SELinux),show that the method can effectively ensure both safety and security properties at runtime.

关键词： active monitoring runtime verification anticipation software safety software security

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