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Timing Error Aware register allocation in TS

Computer Systems Science & Engineering 2022年第1期40卷 273-286页

作者： Sheng Xiao Jing He Xi Yang Heng Zhou Yujie Yuan Information Science and Engineering Department Hunan First Normal UniversityChangsha410205China Computer School Wuhan UniversityWuhan430072China Department of Computer Science Kennesaw State UniversityKennesaw30144-5588USA Hunan Guangyi Experimental Middle School Changsha410205China

Timing speculative(TS)architecture is promising for improving the energy efficiency of microprocessors.Error recovery units,designed for tolerating occasional timing errors,have been used to support a wider range of voltage scaling,therefore to achieve a better energy efficiency.More specifically,the timing error rate,influenced mainly by data forwarding,is the bottleneck for voltage down-scaling in TS processors.In this paper,a new Timing Error Aware register allocation method is proposed.First,we designed the Dependency aware Interference Graph(DIG)construction to get the information of Read after Write(RAW)in programs.To build the construction,we get the disassemble code as input and suppose that there are unlimited registers,the same way as so-called virtual registers in many compilers.Then we change the disassemble codes to the SSA form for each basic block to make sure the registers are defined only once.Based on the DIG construction,registers were real-located to eliminate the timing error,by loosening the RAW dependencies.We con-struct the DIG for each function of the program and sort the edge of DIG by an increasing weight order.Since a smaller weighted-edge value means that its owner nodes have more frequent access in instruction flows,we expect it in different registers with no read-write dependency.At the same time,we make sure that there are no additional new spill codes emerging in our algorithm to minimize the rate of spill code.A high rate of spill code will not only decrease the performance of the system but also increase the unexpected read-write dependency.Next,we reallocate the reg-isters by weight order in turn to loosen the RAW dependencies.Furthermore,we use the NOP operation to pad the instructions with a minimal distance value of 2.Experiment results showed that the average distance of RAW dependencies was increased by over 20%.

关键词： Timing error timing speculative architecture register allocation energy efficiency

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register allocation Algorithm for High-Level Circuit Synthesis for Improved Testability

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Tsinghua Science and Technology 2008年第6期13卷 836-842页

作者：成本茂王红杨士元牛道恒靳洋 Department of Automation Tsinghua University Qingdao Branch Naval Aeronautical Engineering Academy

register allocation in high-level circuit synthesis is important not only for reducing area, delay, and power overheads, but also for improving the testability of the synthesized circuits. This paper presents an improved register allocation algorithm that improves the testability called weighted graph-based balanced register allocation for high-level circuit synthesis. The controllability and observability of the registers and the self-loop elimination are analyzed to form a weighted conflict graph, where the weight of the edge between two nodes denotes the tendency of the two variables to share the same register. Then the modified desaturation algorithm is used to dynamically modify the weights to obtain a final balanced register allocation which improves the testability of the synthesized circuits a higher fault coverage than other algorithms with Tests on some benchmarks show that the algorithm gives less area overhead and even less time delay.

关键词： high-level synthesis （HLS） register allocation testability weighted graph

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Improving on Linear Scan register allocation

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International Journal of Automation and computing 2018年第2期15卷 228-238页

作者： Shahrzad Kananizadeh Kirill Kononenko Department of Computer Science Saarland University Saarbrticken Germany Ecole Normale Superieure/French Institute for Research in Computer Science and Automation (INRIA) Paris France

register allocation is a major step for all compilers. Various register allocation algorithms have been developed over the dec- ades. This work describes a new class of rapid register allocation algorithms and presents experimental data on their behavior. Our re- search encourages the avoidance of graphing and graph-coloring based on the fact that precise graph-coloring is nondeterministic poly- nomial time-complete （NP-complete）, which is not suitable for real-time tasks. In addition, practical graph-coloring algorithms tend to use polynomial-time heuristics. In dynamic compilation environments, their super linear complexity makes them unsuitable for register allocation and code generation. Existing tools for code generation and register allocation do not completely fulfill the requirements of fast compilation. Existing approaches either do not allow for the optimization of register allocation to be achieved comprehensively with a sufficient degree of performance or they require an unjustifiable amount of time and/or resources. Therefore, we propose a new class of register allocation and code generation algorithms that can be performed in linear time. These algorithms are based on the mathematic- al foundations of abstract interpretation and the computation of the level of abstraction. They have been implemented in a specialized library for just-in-time compilation. The specialization of this library involves the execution of common intermediate language （CIL） and low level virtual machine （LLVM） with a focus on embedded systems.

关键词： register allocation just-in-time compilation code generation static analysis dynamic analysis.

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A Novel register allocation Algorithm for Testability

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Tsinghua Science and Technology 2007年第S1期12卷 57-60页

作者：孙强周涛李海军 Department of Computer Science and Technology Harbin Engineering University Department of Mathematics Shaanxi University of Technology

In the course of high-level synthesis of integrate circuit, the hard-to-test structure caused by irrational schedule and allocation reduces the testability of circuit. In order to improve the circuit testability, this paper proposes a weighted compatibility graph (WCG), which provides a weighted formula of compatibility graph based on register allocation for testability and uses improved weighted compatibility clique partition algorithm to deal with this WCG. As a result, four rules for testability are considered simultaneously in the course of register allocation so that the objective of improving the design of testability is acquired. Tested by many experimental results of benchmarks and compared with many other models, the register allocation algorithm proposed in this paper has greatly improved the circuit testability with little overhead on the final circuit area.

关键词： high-level synthesis register allocation testability compatibility graph clique partition algorithm

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