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An IO block array in a radiation-hardened SOI SRAM-based FPGA

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Journal of Semiconductors 2012年第1期33卷 137-143页

作者： Zhao Yan Wu Lihua Han Xiaowei Li Yan Zhang Qianli Chen Liang Zhang Guoquan Li Jianzhong Yang Bo Gao Jiantou Wang Jian Li Ming Liu Guizhai Zhang Feng Guo Xufeng Zhao Kai Stanley L.Chen Yu Fang Liu zhongli Institute of Semiconductors Chinese Academy of Sciences Beijing 100083China

We present an input/output block （lOB） array used in the radiation-hardened SRAM-based field- programmable gate array （FPGA） VS1000, which is designed and fabricated with a 0.5 μm partially depleted silicon-on-insulator （SOI） logic process at the CETC 58th Institute. Corresponding with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input/output buffers and an ESD protection network. A boundary-scan path circuit can be used between the pro- grammable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL/CMOS standard levels. The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic. radiation-hardened designs, including A-type and H-type body-tied transistors and special D-type registers, improve the anti-radiation performance. The ESD protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the core logic caused by the immense current. These design strategies facilitate the design of FPGAs with different ca- pacities or architectures to form a series of FPGAs. The functionality and performance of the IOB array is proved after a functional test. The radiation test indicates that the proposed VS 1000 chip with an IOB array has a total dose tolerance of 100 krad（Si）, a dose survivability rate of 1.5 × 10^11 rad（Si）/s, and a neutron fluence immunity of 1×10^14 n/cm2.

关键词： partially-depleted SOI FPGA IOB radiation-hardened ESD protection

Analysis of single event transient pulse-width in 65 nm commercial radiation-hardened logic cell

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Journal of Semiconductors 2017年第8期38卷 100-104页

作者： Haisong Li Longsheng Wu Bo Yang Yihu Jiang Xi'an Microelectronics Technology Institute

With the critical charge reduced to generate a single event effect （SEE） and high working frequency for a nanometer integrated circuit, the single event effect （SET） becomes increasingly serious for high performance SOC and DSP chips. To analyze the radiation-hardened method of SET for the nanometer integrated circuit, the n＋ guard ring and p＋ guard ring have been adopted in the layout for a 65 nm commercial radiation-hardened standard cell library. The weakest driving capacity inverter cell was used to evaluate the single event transient （SET） pulse-width distribution. We employed a dual-lane measurement circuit to get more accurate SET＇s pulse- width. Six kinds of ions, which provide LETs of 12.5, 22.5, 32.5, 42, 63, and 79.5 MeV-cm2/mg, respectively, have been utilized to irradiate the SET test circuit in the Beijing Tandem Accelerator Nuclear Physics National Laboratory. The testing results reveal that the pulse-width of most SETs is shorter than 400 ps in the range of LETefr from 12.5 ***2/mg to 79.5 MeV-cm2/mg and the pulse-width presents saturation tendency when the effective linear energy transfer （LETeff value is larger than 40 MeV-cm2/mg. The test results also show that the hardened commercial standard cell＇s pulse-width concentrates on 33 to 264 ps, which decreases by 40% compared to the pulse-width of the 65 nm commercial unhardened standard cell.

关键词： single event effect single event transient radiation-hardened guard ring, standard cell library pulsewidth

A radiation-hardened SOl-based FPGA

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Journal of Semiconductors 2011年第7期32卷 136-141页

作者：韩小炜吴利华赵岩李艳张倩莉陈亮张国权李建忠杨波高见头王剑李明刘贵宅张峰郭旭峰陈陵都刘忠立于芳赵凯 Institute of Semiconductors Chinese Academy of Sciences

A radiation-hardened SRAM-based field programmable gate array VS1000 is designed and fabricated with a 0.5μm partial-depletion silicon-on-insulator logic process at the CETC 58th *** new logic cell （LC）,with a multi-mode based on 3-input look-up-table（LUT）,increases logic density about 12%compared to a traditional 4-input *** logic block（LB）,consisting of 2 LCs,can be used in two functional modes：LUT mode and distributed read access memory *** hierarchical routing channel block and switch block can significantly improve the flexibility and routability of the routing *** VS1000 uses a CQFP208 package and contains 392 reconfigurable LCs,112 reconfigurable user I/Os and IEEE 1149.1 compatible with boundary-scan logic for testing and *** function test results indicate that the hardware and software cooperate successfully and the VS1000 works ***,the radiation test results indicate that the VS1000 chip has total dose tolerance of 100 krad（Si）,a dose rate survivability of 1.5×10^（11）rad（Si）/s and a neutron fluence immunity of 1×10^（14） n/cm^2.

关键词： radiation-hardened FPGA partial-depletion SOI reconfigurable LC routing channel block switch block

Research for radiation-hardened high-voltage SOI LDMOS

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Journal of Semiconductors 2019年第5期40卷 41-45页

作者： Yanfei Li Shaoli Zhu Jianwei Wu Genshen Hong Zheng Xu The 58th Research Institute of China Electronics Technology Group Corporation

Based on the silicon-on-insulator(SOI) technology and radiation-hardened silicon gate(RSG) process, a radiation-hardened high-voltage lateral double-diffused MOSFET(LDMOS) device is presented in this paper. With the gate supply voltage of 30 V, the LDMOS device has a gate oxide thickness of 120 nm, and the RSG process is effective in reducing the total ionizing dose(TID) radiation-induced threshold voltage shift. The p-type ion implantation process and gate-enclosed layout topology are used to prevent radiation-induced leakage current through a parasitic path under the bird's beak and at the deep trench corner,and the device is compatible with high-voltage SOI CMOS process. In the proposed LDMOS, the total ionizing dose radiation degradation for the ON bias is more sensitive than the OFF bias. The experiment results show that the SOI LDMOS has a negative threshold voltage shift of 1.12 V, breakdown voltage of 135 V, and off-state leakage current of 0.92 pA/μm at an accumulated dose level of 100 krad(Si).

关键词： radiation-hardened RGS total ion dose threshold voltage shift