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Research on single event transient pulse quenching effect in 90 nm CMOS technology

Science China(Technological Sciences) 2011年第11期54卷 3064-3069页

作者： QIN JunRui CHEN ShuMing LIU BiWei CHEN JianJun LIANG Bin LIU Zheng School of Computer Science National University of Defense Technology Changsha 410073 China

Since single event transient pulse quenching can reduce the SET(single event transient) pulsewidths effectively,the charge collected by passive device should be maximized in order to minimize the propagated *** the perspective of the layout and circuit design,the SET pulsewidths can be greatly inhibited by minimizing the layout spacing and signal propagation delay,which sheds new light on the radiation-hardened ICs(integrated circuits) *** show that the SET pulsewidths of propagation are not in direct proportion to the LET(linear energy transfer) of incident particles,thus the defining of the LET threshold should be noted when SET/SEU(single event upset) occurs for the radiation-hardened *** capability of anti-radiation meets the demand when LET is high but some soft errors may occur when LET is ***,radiation experiments should be focused on evaluating the LET that demonstrates the worst response to the circuit.

关键词： SET propagation radiation hardening by design charge collection charge share quenching

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A novel layout for single event upset mitigation in advanced CMOS SRAM cells

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Science China(Technological Sciences) 2013年第1期56卷 143-147页

作者： QIN JunRui LI DaWei CHEN ShuMing School of Computer Science National University of Defense Technology

A novel layout has been proposed to reduce the single event upset(SEU) vulnerability of SRAM *** 3-D technology computer-aided design(TCAD) simulation analyses show that the proposed layout can recover the upset-state much easier than conventional layout for larger space of PMOS *** the angle incidence,the proposed layout is immune from ion hit in two plans,and is more robust against SEU in other two plans than the conventional *** ability of anti-SEU is enhanced by at least 33% while the area cost reduced by 47%.Consequently,the layout strategy proposed can gain both reliability and area cost benefit simultaneously.

关键词： single event upset layout technique SRAM radiation hardening by design

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A dual redundancy radiation-hardened flip–flop based on a C-element in a 65 nm process

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Journal of Semiconductors 2013年第9期34卷 160-163页

作者：陈刚高博龚敏 School of Physical Science and Technology Sichuan University Microelectronics Technology Key Laboratory of Sichuan Province

A radiation-hardened flip-flop is proposed to mitigate the single event upset （SEU） effect. Immunity was achieved through the use of C-elements and redundant storage elements. It takes advantage of the property of a C-element in which it enters a high impedance mode when its inputs are of different logic values. Redundant storage nodes are then used to drive the C-elements so that a single upset pulse in any storage will be prevented from altering the state of the output of the flip-flop. The flip-flop was implemented using 48 transistors and occupied an area of 30.78 μm2, using 65 nm CMOS process. It consumed 22.6% fewer transistors as compared to the traditional SEU resilient TMR flip-flop.

关键词： single event effect radiation hardening by design triple modular redundancy flip-flop C-element

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