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Performance-Centric Optimization for racetrack memory Based Register File on GPUs

Journal of Computer Science & Technology 2016年第1期31卷 36-49页

作者： Yun Liang Shuo Wang Center for Energy-Efficient Computing and Applications ( CECA) School of Electrical Engineering and Computer Sciences Peking University Beijing 100871 China

The key to high performance for GPU architecture lies in its massive threading capability to drive a large number of cores and enable execution overlapping among threads. However, in reality, the number of threads that can simultaneously execute is often limited by the size of the register file on GPUs. The traditional SRAM-based register file takes up so large amount of chip area that it cannot scale to meet the increasing demand of GPU applications. racetrack memory （RM） is a promising technology for designing large capacity register file on GPUs due to its high data storage density. However, without careful deployment of RM-based register file, the lengthy shift operations of RM may hurt the performance. In this paper, we explore RM for designing high-performance register file for GPU architecture. High storage density RM helps to improve the thread level parallelism （TLP）, but if the bits of the registers are not aligned to the ports, shift operations are required to move the bits to the access ports before they are accessed, and thus the read/write operations are delayed. We develop an optimization framework for RM-based register file on GPUs, which employs three different optimization techniques at the application, compilation, and architecture level, respectively. More clearly, we optimize the TLP at the application level, design a register mapping algorithm at the compilation level, and design a preshifting mechanism at the architecture level. Collectively, these optimizations help to determine the TLP without causing cache and register file resource contention and reduce the shift operation overhead. Experimental results using a variety of representative workloads demonstrate that our optimization framework achieves up to 29% （21% on average） performance improvement.

关键词： register file racetrack memory GPU

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Shape-influenced non-reciprocal transport of magnetic skyrmions in nanoscale channel

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Chinese Physics B 2024年第7期33卷 605-611页

作者：陈杰尧罗佳胡更新王君林李冠祺陈振东陆显扬赵国平刘远吴竞徐永兵 School of Integrated Circuits Guangdong University of TechnologyGuangzhou 510006China School of Physics Engineering and TechnologyUniversity of YorkYork YO105DDUnited Kingdom College of Physics and Electronic Engineering Sichuan Normal UniversityChengdu 610068China Jiangsu Provincial Key Laboratory of Advanced Photonic and Electronic Materials School of Electronic Science and EngineeringNanjing UniversityNanjing 210093China

Skyrmions, with their vortex-like structures and inherent topological protection, play a pivotal role in developing innovative low-power memory and logic devices. The efficient generation and control of skyrmions in geometrically confined systems are crucial for the development of skyrmion-based spintronic devices. In this study, we focus on investigating the non-reciprocal transport behavior of skyrmions and their interactions with boundaries of various shapes. The shape of the notch structure in the nanotrack significantly affects the dynamic behavior of magnetic skyrmions. Through micromagnetic simulation, the non-reciprocal transport properties of skyrmions in nanowires with different notch structures are investigated in this work.

关键词： skyrmion micromagnetic simulation racetrack memory

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Realization of skyrmion shift register

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Science Bulletin 2024年第15期69卷 2370-2378页

作者： Le Zhao Chensong Hua Chengkun Song Weichao Yu Wanjun Jiang State Key Laboratory of Low-Dimensional Quantum Physics and Department of Physics Tsinghua UniversityBeijing 100084China Frontier Science Center for Quantum Information Tsinghua UniversityBeijing 100084China State Key Laboratory of Surface Physics and Institute for Nanoelectronic Devices and Quantum Computing Fudan UniversityShanghai 200433China Zhangjiang Fudan International Innovation Center Fudan UniversityShanghai 201210China

The big data explosion demands novel data storage technology. Among many different approaches, solitonic racetrack memory devices hold great promise for accommodating nonvolatile and low-power functionalities. As representative topological solitons, magnetic skyrmions are envisioned as potential information carriers for efficient information processing. While their advantages as memory and logic elements have been vastly exploited from theoretical perspectives, the corresponding experimental efforts are rather limited. These challenges, which are key to versatile skyrmionic devices, will be studied in this work. Through patterning concaved surface topography with designed arrays of indentations on standard Si/SiO_(2) substrates, we demonstrate that the resultant non-flat energy landscape could lead to the formation of hexagonal and square skyrmion lattices in Ta/CoFeB/MgO multilayers. Based on these films, one-dimensional racetrack devices are subsequently fabricated, in which a long-distance deterministic shifting of skyrmions between neighboring indentations is achieved at room temperature. Through separating the word line and the bit line, a prototype shift register device, which can sequentially generate and precisely shift complex skyrmionic data strings, is presented. The deterministic writing and longdistance shifting of skyrmionic bits can find potential applications in transformative skyrmionic memory,logic as well as the in-memory computing devices.

关键词： Skyrmions racetrack memory Spintronics Surface-topography Indentations

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Current-driven transformations of a skyrmion tube and a bobber in stepped nanostructures of chiral magnets

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Science China(Physics,Mechanics & Astronomy) 2021年第2期64卷 105-110页

作者： Jin Zhu YaoDong Wu QiYang Hu LingYao Kong Jin Tang MingLiang Tian HaiFeng Du Anhui Province Key Laboratory of Condensed Matter Physics at Extreme Conditions High Magnetic Field Laboratory of Chinese Academy of SciencesUniversity of Science and Technology of ChinaHefei230031China Universities Joint Key Laboratory of Photoelectric Detection Science and Technology in Anhui Province Hefei Normal UniversityHefei230601China School of Physics and Materials Science Anhui UniversityHefei230601China Institutes of Physical Science and Information Technology Anhui UniversityHefei230601China

Magnetic skyrmion tubes and bobbers are two types of different nanoscale spin configurations that can coexist in nanostructures of chiral *** are then proposed to be utilized as binary bits to build racetrack memory *** ability to manipulate the two magnetic objects controllably by current in nanostructures is the prerequisite to realize the ***,we demonstrate by numerical simulations that a magnetic bobber and a skyrmion tube can be transformed to each other using spinpolarized current in nanostripes with stepped *** also show such stepped nanostructures can be readily applied as the write head for the skyrmion-bobber-based racetrack memory.

关键词： skyrmion bobber racetrack memory stepped nanostructures chiral magnets

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