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SDN-Based Switch Implementation on Network processors

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Communications and Network 2013年第3期5卷 434-437页

作者： Yunchun Li Guodong Wang School of Computer Science and Engineering BeiHang University Beijing China

Virtualization is the key technology of cloud computing. Network virtualization plays an important role in this field. Its performance is very relevant to network virtualizing. Nowadays its implementations are mainly based on the idea of Software Define Network (SDN). Open vSwitch is a sort of software virtual switch, which conforms to the OpenFlow protocol standard. It is basically deployed in the Linux kernel hypervisor. This leads to its performance relatively poor because of the limited system resource. In turn, the packet process throughput is very *** this paper, we present a Cavium-based Open vSwitch implementation. The Cavium platform features with multi cores and couples of hard ac-celerators. It supports zero-copy of packets and handles packet more quickly. We also carry some experiments on the platform. It indicates that we can use it in the enterprise network or campus network as convergence layer and core layer device.

关键词： SDN Open vSwitch Network processors OpenFlow

Grounding Technique Quells EMI from Fast processors

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电源世界 2003年第12期 61-62页

作者： David G.Morrison

With microprocessor clock speeds rising above 1 GHz, theCPU’s heatsink comes under increasing scrutiny as a source ofelectromagnetic interference (EMI). Often, this problem isn’ taddressed until after the microprocessor has been designed inand the product is undergoing EMI tests. If EMI problems arediscovered at that point, they’re addressed with Band—Aid solutions,such as adding shielding hardware. Naturally, such fixesslow product development and add cost. Moreover, theymay be ineffective in future product spins with newer processors.

关键词： processors hardware addressed shielding adding clock until comes aperture titled

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processors处理器

个人电脑 2004年第1期10卷 89-89页

2003年里，我们在处理器市场上看到了一幕幕重头戏的上演,基于Hyper Threading技术的Pentium4处理器、Pentium 4 EE、AMD Athlon 64、AMD Athlon 64FX系列，这些新产品的快速推出让人有目不暇接的感觉。

关键词： processors 微处理器体系结构 CPU 纳米制造工艺

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处理器processors

个人电脑 2004年第1期10卷 110-110页

PhiBench 2.0: characterizing data analytics workloads on Intel Knights Landing

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High Technology Letters 2019年第2期25卷 121-128页

作者：解壁伟 Zhan Jianfeng Wang Lei Zhang Lixin Institute of Computing Technology Chinese Academy of SciencesBeijing 100190P.R.China University of Chinese Academy of Sciences Beijing 100049P.R.China

With high computational capacity, e.g. many-core and wide floating point SIMD units, Intel Xeon Phi shows promising prospect to accelerate high-performance computing(HPC) applications. But the application of Intel Xeon Phi on data analytics workloads in data center is still an open question. Phibench 2.0 is built for the latest generation of Intel Xeon Phi(KNL, Knights Landing), based on the prior work PhiBench(also named BigDataBench-Phi), which is designed for the former generation of Intel Xeon Phi(KNC, Knights Corner). Workloads of PhiBench 2.0 are delicately chosen based on BigdataBench 4.0 and PhiBench 1.0. Other than that, these workloads are well optimized on KNL, and run on real-world datasets to evaluate their performance and scalability. Further, the microarchitecture-level characteristics including CPI, cache behavior, vectorization intensity, and branch prediction efficiency are analyzed and the impact of affinity and scheduling policy on performance are investigated. It is believed that the observations would help other researchers working on Intel Xeon Phi and data analytics workloads.

关键词： Intel Xeon Phi data analytics workloads characterization Knights Landing(KNL) many core x86 processors

SimNP: A Flexible Platform for the Simulation of Network Processing Systems

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Communications and Network 2010年第4期2卷 207-215页

作者： David Bermingham Zhen Liu Xiaojun Wang 不详

Network processing plays an important role in the development of Internet as more and more complicated applications are deployed throughout the network. With the advent of new platforms such as network processors (NPs) that incorporate novel architectures to speedup packet processing, there is an increasing need for an efficient method to facilitate the study of their performance. In this paper, we present a tool called SimNP, which provides a flexible platform for the simulation of a network processing system in order to provide information for workload characterization, architecture development, and application implementation. The simulator models several architectural features that are commonly employed by NPs, including multiple processing engines (PEs), integrated network interface and memory controller, and hardware accelerators. ARM instruction set is emulated and a simple memory model is provided so that applications implemented in high level programming language such as C can be easily compiled into an executable binary using a common compiler like gcc. Moreover, new features or new modules can also be easily added into this simulator. Experiments have shown that our simulator provides abundant information for the study of network processing systems.

关键词： Network processors Sim NP

THE FEATURES OF A PARALLEL INFERENCE MACHINE EPIM

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Chinese Science Bulletin 1987年第23期32卷 1585-1589页

作者：谭小南张祥高庆狮 Institute of Computing Technology Academia Sinica Beijing

The paralld inference machine which supports the parallel execution of logic programs is one of the components forming the kernel of the fifth generation computer systems. The design of the architecture of parallel in... 详细信息

关键词： execution kernel locality processors inference programs overhead performing structured hardware

An Instruction-Level Analytical Power Model for Designing the Low Power Systems on a Chip

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An Instruction-Level Analytical Power Model for Designing th...

Dahlia: JXTA Based Grid Computing Framework

2005 6th International Conference on ASIC

作者： Rong LUO Hong LUO Huazhong YANG Yuan XIE Dept.of Electronic Engineering Tsinghua University Dept.of Computer Science & Engineering Pennsylvania State University University ParkPA16802USA

＜正＞In this paper,an instruction-level analytical power model for the low power Systems on a Chip（SoC） is proposed. The inter-instruction effects are obtained with combining different instructions for program running in a processor,such as DSP,CPU for Embedded *** in base costs as different operands and addresses are also ***,power consumption of one section of DSP program is measured and compared with the estimated value by our model,which shows that the proposed model is simp le and effective for estimating the power consumption of program and it is useful for further software/hardware co-design of SoC.

关键词： Power Model SoC Instruction-level processors

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Dahlia: JXTA Based Grid Computing Framework

作者： Manoj Shakya 湖南大学

学位级别：硕士

This report presents the Dahlia grid computing framework. Dahlia is implemented using the Java programming language and uses peer-to-peer technology provided by the Project JXTA protocols. Project JXTA defines a set of communication protocols allowing any network connected device to communicate in a peer-to-peer manner.The system consists of broker, manager, executor and task submitter. The task submitter is associated with the developer section. Whenever a developer has to submit a bundle of tasks, it notifies the task submitter. The task submitter then connects to the broker and tells the broker that it has some jobs to be processed. The broker analyses the set of managers and notifies the managers to activate their executors. Those managers notified by the broker then activate their executors. Now each executor activated by their managers tries to connect the task submitter. After establishing the connection to the task submitter, the executor requests for the job. The executor executes the job assigned by the task submitter and returns the result to the task submitter. If no executor requests for the jobs, the task submitter keeps on sending the signal to the broker saying that it has some tasks to be processed.The system is not self configuring. The server should start an application from dahlia system that creates a Dahlia group. Any computer volunteering their computing power will run an application called Executor. Before anyone runs executor, there must be some mangers running in the system. The system offers a framework for the development of applications solving parameter sweep applications type of problems but can also be used for other kinds of problems. The framework generates the number of system threads and sends them to the executors to execute. Furthermore, the system makes it extremely easy for users to write grid applications that use the dahlia grid system.

关键词： processors Scheduling broker runtime applet ATLAS scalability enable running communicate