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A frequency servo SoC with output power stabilization loop technology for miniaturized atomic clocks

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Journal of Semiconductors 2024年第6期45卷 13-22页

作者： Hongyang Zhang Xinlin Geng Zonglin Ye Kailei Wang Qian Xie Zheng Wang School of Integrated Circuit Science and Engineering University of Electronic Science and Technology of ChinaChengdu 611731China

A frequency servo system-on-chip(FS-SoC)featuring output power stabilization technology is introduced in this study for high-precision and miniaturized cesium(Cs)atomic clocks.The proposed power stabilization loop(PSL)technique,incorporating an off-chip power detector(PD),ensures that the output power of the FS-SoC remains stable,mitigating the impact of power fluctuations on the atomic clock's stability.Additionally,a one-pulse-per-second(1PPS)is employed to syn-chronize the clock with GPS.Fabricated using 65 nm CMOS technology,the measured phase noise of the FS-SoC stands at-69.5 dBc/Hz@100 Hz offset and-83.9 dBc/Hz@1 kHz offset,accompanied by a power dissipation of 19.7 mW.The Cs atomic clock employing the proposed FS-SoC and PSL obtains an Allan deviation of 1.7×10^(-11) with 1-s averaging time.

关键词： CMOS technology atomic clock phase-locked loop output power stabilization 1PPS

Generation of visible Raman operation laser by a fiber electro-optical modulator feedback loop

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Chinese Optics Letters 2024年第2期22卷 180-185页

作者：李睿睿叶蔚然陈一龙陈树谦亓文昊崔金明黄运锋李传锋郭光灿 CAS Key Laboratory of Quantum Information University of Science and Technology of ChinaHefei 230026China CAS Center for Excellence in Quantum Information and Quantum Physics University of Science and Technology of ChinaHefei 230026China Hefei National Laboratory University of Science and Technology of ChinaHefei 230088China

phase-coherent multi-tone lasers play a critical role in atomic,molecular,and optical physics.Among them,the Raman opeartion laser for manipulating atomic hyperfine qubits requires gigahertz bandwidth and low phase noise to retain long-term coherence.Raman operation lasers generated by directly modulated and frequency-multipled infrared lasers are compact and stable but lack feedback control to actively suppress the phase noise,which limits their performance in practical applications.In this work,we employ a fiber electro-optical modulator driven by a voltage-controlled oscillator(VCO)to modulate a monochromatic laser and employ a second-harmonic generation process to convert it to the visible domain,where the beat note of the Raman operation laser is stabilized by controlling the output frequency of VCO with a digital phase-locked loop(PLL).The low-frequency phase noise is effectively suppressed compared to the scheme without active feedback and it reaches-80 d Bc/Hz@5 k Hz with a 20 k Hz loop bandwidth.Furthermore,this compact and robust scheme effectively reduces the system's complexity and cost,which is promising for extensive application in atomic,molecular,and optical physics.

关键词： phase-coherent laser quantum information trapped ion stimulated Raman transition phase-locked loop

DC offset rejection in a frequency-fixed second-order generalized integrator-based phase-locked loop for single-phase grid-connected applications

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Protection and Control of Modern Power Systems 2022年第1期7卷 1-13页

作者： Issam A.Smadi Bayan H.Bany Fawaz Electrical Engineering Department Jordan University of Science and TechnologyIrbid 22110Jordan

Fast and accurate monitoring of the phase,amplitude,and frequency of the grid voltage is essential for single-phase grid-connected converters.The presence of DC offset in the grid voltage is detrimental to not only grid synchronization but also the closed-loop stability of the grid-connected converters.In this paper,a new synchronization method to mitigate the effect of DC offset is presented using arbitrarily delayed signal cancelation(ADSC)in a second-order generalized integrator(SOGI)phase-locked loop(PLL).A frequency-fixed SOGI-based PLL(FFSOGI-PLL)is adopted to ensure better stability and to reduce the complexity compared with other SOGI-based PLLs.A small-signal model of the proposed PLL is derived for the systematic design of proportional-integral(PI)controller gains.The effects of frequency variation and ADSC on the proposed PLL are considered,and correction methods are adopted to accurately estimate grid information.The simulation results are presented,along with comparisons to other single-phase PLLs in terms of settling time,peak frequency,and phase error to validate the proposed PLL.The dynamic performance of the proposed PLL is also experimentally validated.Overall,the proposed PLL has the fastest transient response and better dynamic performance than the other PLLs for almost all performance indices,offering an improved solution for precise grid synchronization in single-phase applications.

关键词： Grid integration Virtual microgrid DC offset mitigation Grid synchronization phase-locked loop Second-order generalized integrator

Short locking time and low jitter phase-locked loop based on slope charge pump control

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Journal of Semiconductors 2010年第10期31卷 79-85页

作者：郭仲杰刘佑宝吴龙胜汪西虎唐威 Xi'an Microelectronic Technology Institute

A novel structure of a phase-locked loop （PLL） characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector （PFD） to implement adaptive bandwidth control. This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL. First, the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter. Then, when the output pulse of the PFD is larger than a minimum value, the charge pump current is increased linearly by the slope current control to ensure a shorter locking time and a lower jitter. Additionally, temperature variation is attenuated with the temperature compensation in the charge pump current design. The proposed PLL has been fabricated in a kind of DSP chip based on a 0.35 μm CMOS process. Comparing the characteristics with the classical PLL, the proposed PLL shows that it can reduce the locking time by 60% with a low peak-to-peak jitter of 0.3% at a wide operation temperature range.

关键词： phase-locked loop loop bandwidth phase margin phase frequency detector slope charge pump current

A multiple-pass ring oscillator based dual-loop phase-locked loop

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Journal of Semiconductors 2009年第10期30卷 132-136页

作者：陈丹凤任俊彦邓晶晶李巍李宁 State Key Laboratory of ASIC & System Fudan University

A dual-loop phase-locked loop（PLL）for wideband operation is proposed.The dual-loop architecture combines a coarse-tuning loop with a fine-tuning one,enabling a wide tuning range and low voltage-controlled oscillator（VCO）gain without poisoning phase noise and reference spur suppression performance.An analysis of the phase noise and reference spur of the dual-loop PLL is emphasized.A novel multiple-pass ring VCO is designed for the dual-loop application.It utilizes both voltage-control and current-control simultaneously in the delay cell. The PLL is fabricated in Jazz 0.18-μm RF CMOS technology.The measured tuning range is from 4.2 to 5.9 GHz.It achieves a low phase noise of–99 dBc/Hz@1 MHz offset from a 5.5 GHz carrier.

关键词： coarse-tuning dual-loop fine-tuning phase-locked loop phase noise

Design of radiation hard phase-locked loop at 2.5 GHz using SOS-CMOS

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Journal of Systems Engineering and Electronics 2009年第6期20卷 1159-1166页

作者： Partha Pratim Ghosh Jung Sungyong Dept. of Electrical Engineering Univ. of Texas at Arlington Arlington TX 76019 USA

A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.

关键词： phase-locked loop radiation hard self-bias silicon on sapphire complementary metal-oxidesemiconductor.

A 3.96 GHz phase-locked loop for mode-1 MB-OFDM UWB hopping carrier generation

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Journal of Semiconductors 2009年第7期30卷 91-95页

作者：郑永正李伟男夏玲琍黄煜梅洪志良 State Key Laboratory of ASIC & System Fudan University

A fully integrated phase-locked loop（PLL） is presented for a single quadrature output frequency of 3.96 GHz.The proposed PLL can be applied to mode-1 MB-OFDM UWB hopping carrier generation.An adaptive frequency calibration loop is incorporated into the PLL.The capacitance area in the loop filter is largely reduced through a capacitor multiplier.Implemented in a CMOS process, this PLL draws 13.0 mA current from a single 1.2 V supply while occupying 0.55 mm2 die area.Measurement results show that the PLL achieves a phase noise of-70 dBc/Hz at 10 kHz offset and-113 dBc/Hz at 1 MHz offset.The integrated RMS jitter from 1 kHz to 10 MHz is 2.2 ps.The reference spur level is less than-68 dBc.

关键词： phase-locked loop adaptive frequency calibration loop filter CMOS UWB

A low spur,low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology

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Journal of Semiconductors 2011年第3期32卷 100-104页

作者：梅年松孙瑜陆波潘姚华黄煜梅洪志良 State Key Laboratory of ASIC & Systems Fudan University

This paper presents a 10-GHz low spur and low jitter phase-locked loop（PLL）.An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL.We also discuss the methodology to optimize the high frequency prescaler’s noise and the charge pump’s current mismatch.The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply.The measured integrated RMS jitter is 757 fs（1 kHz to 10 MHz）;the phase noise is-89 and-118.1 dBc/Hzat 10kHz and 1 MHz frequency offset,respectively;and the reference frequency spur is below -77 dBc.The chip size is 0.32 mm2 and the power consumption is 30.6 mW.

关键词： phase-locked loop VCO charge pump current mismatch

Design of a high performance CMOS charge pump for phase-locked loop synthesizers

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Journal of Semiconductors 2011年第7期32卷 103-107页

作者：李智群郑爽爽侯凝冰 Institute of RF-& OE-ICs Southeast University RFIC and System Engineering Research Center of the Ministry of Education of China Southeast University School of Integrated Circuits Southeast University

A new high performance charge pump circuit is designed and realized in 0.18μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range.Furthermore,a method of adding a precharging current source is proposed to increase the initial charge current,which will speed up the settling time of CPPLLs.Test results show that the current mismatching can be less than 0.4%in the output voltage range of 0.4 to 1.7 V,with a charge pump current of 100μA and a precharging current of 70μA.The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.

关键词： charge pump current mismatch rail-to-rail operational amplifier phase-locked loop