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Approximation algorithm for multiprocessor parallel job scheduling

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Journal of Central South University of Technology 2002年第4期9卷 267-272页

作者：陈松乔黄金贵陈建二 College of Information Engineering Central South University

P k |fix| C max problem is a new scheduling problem based on the multiprocessor parallel job, and it is proved to be NP hard problem when k ≥3. This paper focuses on the case of k =3. Some new observations and new techniques for P 3 |fix| C max problem are offered. The concept of semi normal schedulings is introduced, and a very simple linear time algorithm Semi normal Algorithm for constructing semi normal schedulings is developed. With the method of the classical Graham List Scheduling, a thorough analysis of the optimal scheduling on a special instance is provided, which shows that the algorithm is an approximation algorithm of ratio of 9/8 for any instance of P 3|fix| C max problem, and improves the previous best ratio of 7/6 by ***.

关键词： multiprocessor parallel job scheduling approximation algorithm NP-hard problem

Design and optimization for multiprocessor interactive GPU

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The Journal of China Universities of Posts and Telecommunications 2014年第3期21卷 85-97页

作者： DENG Jun-yong LI Tao JIANG Lin HAN Jun-gang SHEN Xu-bang School of Micro-electronics Xidian University School of Electronic Engineering Xi’an University of Posts and Telecommunications

In order to achieve maximization of parallelism, effective distribution of rendering tasks, balance between performance and flexibility in graphics processing pipeline, this article presents design, performance analysis and optimization for multi-core interactive graphics processing unit （MIGPU）. This processor integrates twelve processing cores with specific instruction set architecture and many sophisticated application-specific accelerators into a 3D graphics engine. It is implemented on XC6VLX550T field programmable gate array （FPGA）. MIGPU supports OpenGL2.0 with programmable front-end processor, vertex shader, plane clipper, geometry transformer, three-D clippers and pixel shaders. For boosting the performance of MIGPU, the relationship model is established between primitive types, vertices, pixels, and the effect of culling, clipping, and memory access, and shows a way to improve the speed up of the graphics pipeline. It is capable of assigning graphics rendering tasks to different processors for efficiency and flexibility. The pixel filling rate can reach to 40 Mpixel/s at its peak performance.

关键词： multiprocessor graphics processing unit (GPU) performance optimization parallelism

Dynamic Load Balancing Based on Restricted Multicast Tree in Homogeneous multiprocessor Systems

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Journal of Beijing Institute of Technology 2008年第2期17卷 184-188页

作者：刘滨石峰高玉金 School of Computer Science and Technology Beijing Institute of Technology

To decrease the cost of exchanging load information among processors, a dynamic load-balancing （DLB） algorithm which adopts multieast tree technology is proposed. The muhieast tree construction rules are also proposed to avoid wrongly transferred or redundant DLB messages due to the overlapping of multicast trees. The proposed DLB algorithm is distributed controlled, sender initiated and can help heavily loaded processors with complete distribution of redundant loads with minimum number of executions. Experiments were executed to compare the effects of the proposed DLB algorithm and other three ones, the results prove the effectivity and practicability of the proposed algorithm in dealing with great scale compute-intensive tasks.

关键词： dynamic load balancing (DLB) multicast tree rule message multiprocessor

YH-MCS Reconstructable Fault-tolerant multiprocessor Control System

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High Technology Letters 1996年第2期2卷 17-20页

作者：肖刚 Dept.of Auto-control National University of Defense TechnologyChangsha 410073P.R.China)

FMS is the basic and frontier technology of advanced *** critical compo-nent is FMS control *** fault-tolerant multiprocessor control system,YH-MCS,is the result of the research on the high-performance and high-reliable FMS con-trol *** paper describes its architecture,technology characteristics,academic valueand application potentiality.

关键词： FMS multiprocessor Fault-tolerance

A Particle Swarm Optimization to Minimize Makespan for a Four-Stage multiprocessor Open Shop with Dynamic Job Release Time

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World Journal of Engineering and Technology 2015年第3期3卷 78-83页

作者： Hui-Mei Wang Fuh-Der Chou Department of Hotel Management Vanung University Taoyuan Chinese Taipei Department of Industrial Management Chien Hsin University Taoyuan Chinese Taipei

This paper considers the scheduling problem observed in chip sorting operation of LED manufacturing, where each lot (job) with release time have four operations to be processed on a set of processing stages without pre-determined necessary route. Each stage has one and more identical sorting machines. The sorting machines scheduling problem can be treated as a four-stage multiprocessor open shop problem with dynamic job release, and the objective is minimizing the makespan in the paper. This problem is formulated into a mixed integer programming (MIP) model and empirically shows its computational intractability. Due to the computational intractability, a particle swarm optimization (PSO) algorithm is proposed. A series of computational experiments are conducted to evaluate the performance of the proposed PSO in comparison with exact solution on various small-size problem instances. The results show that the PSO algorithm could finds most optimal or better solutions in one second.

关键词： Open Shop multiprocessor Makespan Particle Swarm Optimization

CFP:A Coherence-Free Processor Design

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Journal of Computer Science & Technology 2024年第1期39卷 99-102页

作者：杨光诺 Mount Gilead OH 43338U.S.A

This paper presents the design of a Coherence-Free Processor(CFP)that enables a scalable multiprocessor by eliminating cache coherence operations in both hardware and *** CFP uses a coherence-free cache(CFC)that can improve the cost-effectiveness and performance-effectiveness of the existing multiprocessors for commonly used *** CFC is feasible because not all program data that reside in a multiprocessor cache need to be accessed by other processors,and private caches at level 1(L1)and level 2(L2)facilitate this method of *** programs are specifically designed to protect their data from modification by other *** data that are modified but not shared with other tasks do not require a coherence *** processors reduces the multitasking queue,reducing elapsed *** execution replaces concurrent execution.

关键词： multiprocessor multitasking cache coherence snoopy

Study and Analysis of Bus Arbitration Mechanism in PI-MPS multiprocessor System

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Journal of Harbin Institute of Technology(New Series) 1997年第3期4卷 26-29页

作者：王申科冯锡栋暴建民李斌杨孝宗

This paper presents the mechanism of the bus arbitration in PI-MPS multiprocessor sys-tem,describes encode approach,arbiter timing states and uniqueness of master modular ininterconnection bus,and measures and analyse... 详细信息

关键词： multiprocessor system distributed system bus

Design of ANN Based Non-Linear Network Using Interconnection of Parallel Processor

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Computer Systems Science & Engineering 2023年第9期46卷 3491-3508页

作者： Anjani Kumar Singha Swaleha Zubair Areej Malibari Nitish Pathak Shabana Urooj Neelam Sharma Department of Computer Science Aligarh Muslim UniversityAligarh202002India Department of Industrial and Systems Engineering College of EngineeringPrincess Nourah bint Abdulrahman UniversityP.O.Box 84428Riyadh11671Saudi Arabia Department of Information Technology Bhagwan Parshuram Institute of Technology(BPIT)GGSIPUNew Delhi110078India Department of Electrical Engineering College of EngineeringPrincess Nourah bint Abdulrahman UniversityP.O.Box 84428Riyadh11671Saudi Arabia Department of Artificial Intelligence&Machine Learning Maharaja Agrasen Institute of Technology(MAIT)GGSIPUNew Delhi110086India

Suspicious mass traffic constantly evolves,making network behaviour tracing and structure more *** networks yield promising results by considering a sufficient number of processing elements with strong interconnections between *** offer efficient computational Hopfield neural networks models and optimization constraints used by undergoing a good amount of parallelism to yield optimal *** neural network(ANN)offers optimal solutions in classifying and clustering the various reels of data,and the results obtained purely depend on identifying a *** this research work,the design of optimized applications is presented in an organized *** addition,this research work examines theoretical approaches to achieving optimized results using *** mainly focuses on designing *** optimizing design approach of neural networks analyzes the internal process of the neural *** in developing the network are based on the interconnections among the hidden nodes and their learning *** methodology is proven best for nonlinear resource allocation problems with a suitable design and complex *** ANN proposed here considers more or less 46k nodes hidden inside 49 million connections employed on full-fledged parallel *** proposed ANN offered optimal results in real-world application problems,and the results were obtained using MATLAB.

关键词： Artificial neural network(ANN) multiprocessor hidden node nonlinear optimization parallel processing

DEAM: Decoupled, Expressive, Area-Efficient Metadata Cache

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Journal of Computer Science & Technology 2014年第4期29卷 679-691页

作者：刘鹏方磊黄巍 CCF IEEE Department of Information Science and Electronic Engineering Zhejiang University State Key Laboratory of Mathematical Engineering and Advanced Computing ACM Department of Electrical and Computer Engineering University of Rochester NY 14627-0231 U.S.A.

Chip multiprocessor presents brand new opportunities for holistic on-chip data and coherence management solutions. An intelligent protocol should be adaptive to the fine-grain accessing behavior. And in terms of storage of metadata, the size of conventional directory grows as the square of the number of processors, making it very expensive in large-scale systems. In this paper, we propose a metadata cache framework to achieve three goals： 1） reducing the latency of data access and coherence activities, 2） saving the storage of metadata, and 3） providing support for other optimization techniques. The metm：lata is implemented with compact structures and tracks the dynamically changing access pattern. The pattern information is used to guide the delegation and replication of decoupled data and metadata to allow fast access. We also use our metadata cache as a building block to enhance stream prefetching. Using detailed execution-driven simulation, we demonstrate that our protocol achieves an average speedup of 1.12X compared with a shared cache protocol with 1/5 of the storage of metadata.

关键词： cache directory multiprocessor