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HSCS:a hybrid shared cache scheduling scheme for multiprogrammed workloads

Frontiers of Computer Science 2018年第6期12卷 1090-1104页

作者： Jingyu ZHANG Chentao WU Dingyu YANG Yuanyi CHEN Xiaodong MENG Liting XU Minyi GUO Department of Computer Science and Engineering Shanghai Jiao Tong UniversityShanghai 200240China Hunan Provincial Key Laboratory of Intelligent Processing of Big Data on Transportation School of Computer and Communication EngineeringChangsha University of Science and TechnologyChangsha 410004China School of Electronics and Information Shanghai Dianji UniversityShanghai 200240China

The traditional dynamic random-access memory (DRAM) storage medium can be integrated on chips via modern emerging 3D-stacking technology to architect a DRAM shared cache in multicore systems. Compared with static random-access memory (SRAM), DRAM is larger but slower. In the existing research, a lot of work has been devoted to improving the workload performance using SRAM and stacked DRAM together in shared cache systems, ranging from SRAM structure improvement to optimizing cache tags and data access. However, little attention has been paid to designing a shared cache scheduling scheme for multiprogrammed workloads with different memory footprints in multicore systems. Motivated by this, we propose a hybrid shared cache scheduling scheme that allows a multicore system to utilize SRAM and 3D-stacked DRAM efficiently, thus achieving better workload performance. This scheduling scheme employs (1) a cache monitor, which is used to collect cache statistics; (2) a cache evaluator, which is used to evaluate the cache information during the process of programs being executed; and (3) a cache switcher, which is used to self-adaptively choose SRAM or DRAM shared cache modules. A cache data migration policy is naturally developed to guarantee that the scheduling scheme works correctly. Extensive experiments are conducted to evaluate the workload performance of our proposed scheme. The experimental results showed that our method can improve the multiprogrammed workload performance by up to 25% compared with state-of-the-art methods (including conventional and DRAM cache systems).

关键词： multicore system shared cache workload performance

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Dual-Port Content Addressable Memory for Cache Memory Applications

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Computers, Materials & Continua 2022年第3期70卷 4583-4597页

作者： Allam Abumwais Adil Amirjanov Kaan Uyar Mujahed Eleyat Department of Computer Engineering Near East UniversityNicosiaN.Cyprus via Mersin-10Turkey Computer systems Engineering Arab American UniversityJenin240Palestine

multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory *** paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual port content addressable memory(DPCAM).In addition,it proposes a new replacement algorithm based on hardware which is called a near-far access replacement algorithm(NFRA)to reduce the cost overhead of the cache controller and improve the cache access *** experimental results indicated that the latency for write and read operations are significantly less in comparison with a set-associative cache ***,it was shown that a latency of a read operation is nearly constant regardless of the size of ***,an estimation of the power dissipation showed that DPCAM consumes about 7%greater than a set-associative cache memory of the same *** results encourage for embedding DPCAM within the multicore processors as a small shared cache memory.

关键词： multicore system content addressable memory dual port CAM cache controller set-associative cache power dissipation

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