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Design for Testability Features of Godson-3 multicore Microprocessor

Journal of Computer Science & Technology 2011年第2期26卷 302-313页

作者：齐子初刘慧李向库胡伟武 Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Computing Technology Chinese Academy of Sciences Loongson Technologies Corporation Limited

This paper describes the design for testability （DFT） challenges and techniques of Godson-3 microprocessor, which is a scalable multicore processor based on the scalable mesh of crossbar （SMOC） on-chip network and targets high-end applications. Advanced techniques are adopted to make the DFT design scalable and achieve low-power and low-cost test with limited IO resources. To achieve a scalable and flexible test access, a highly elaborate test access mechanism （TAM） is implemented to support multiple test instructions and test modes. Taking advantage of multiple identical cores embedding in the processor, scan partition and on-chip comparisons are employed to reduce test power and test time. Test compression technique is also utilized to decrease test time. To further reduce test power, clock controlling logics are designed with ability to turn off clocks of non-testing partitions. In addition, scan collars of CACHEs are designed to perform functional test with low-speed ATE for speed-binning purposes, which poses low complexity and has good correlation results.

关键词： DFT (design for testability) TAM (test access mechanism) multicore processor low power test

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Wide Operational Range processor Power Delivery Design for Both Super-Threshold Voltage and Near-Threshold Voltage Computing

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Journal of Computer Science & Technology 2016年第2期31卷 253-266页

作者： Xin He Gui-Hai Yan Yin-He Han Xiao-Wei Li State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100049 China

The load power range of modern processors is greatly enlarged because many advanced power management techniques are employed, such as dynamic voltage frequency scaling, Turbo Boosting, and near-threshold voltage （NTV） technologies. However, because the efficiency of power delivery varies greatly with different load conditions, conventional power delivery designs cannot maintain high efficiency over the entire voltage spectrum, and the gained power saving may be offset by power loss in power delivery. We propose SuperRange, a wide operational range power delivery unit. SuperRange complements the power delivery capability of on-chip voltage regulator and off-chip voltage regulator. On top of SuperRange, we analyze its power conversion characteristics and propose a voltage regulator （VR） aware power management algorithm. Moreover, as more and more cores have been integrated on a singe chip, multiple SuperRange units can serve as basic building blocks to build, in a highly scalable way, more powerful power delivery subsystem with larger power capacity. Experimental results show SuperRange unit offers lx and 1.3x higher power conversion efficiency （PCE） than other two conventional power delivery schemes at NTV region and exhibits an average 70% PCE over entire operational range. It also exhibits superior resilience to power-constrained systems.

关键词： voltage regulator power delivery near-threshold computing multicore processor

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Architecture Level Thermal Modeling for Multi-Core Systems using Subspace System Method

Architecture Level Thermal Modeling for Multi-Core Systems u...

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2009 IEEE 8th International Conference on ASIC(ASICON 2009)

作者： Thom Jefferson A.Eguia Sheldon X.-D.Tan Eduardo H.Pacheco Murli Tirumala Department of Electrical En-gineering University of California RiversideCA 92521USA. Intel Corporation 2200 Mission Col-lege BlvdSanta ClaraCA 95052

This paper proposes a new architecture-level thermal modeling method to address the emerging thermal related analysis and optimization problem for high-performance multi-core microprocessor *** new approach,called Thermsid,builds the thermal behavioral models from the measured or simulated thermal and power information at the architecture *** builds the thermal models by first generating a Hankel matrix of Markov parameters,from which state matrices are obtained through minimum square *** to existing behavioral thermal modeling algorithms,the proposed method is much more general as it does not require step temperature responses,leading to greater flexibility during the modeling *** results on a real quad-core microprocessor show that Thermsid provides accurate thermal behavioral models comparable existing approaches.

关键词： Thermal analysis architecture thermal modeling multicore processor

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面向多核处理器的外内核操作系统研究

面向多核处理器的外内核操作系统研究

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作者：刘群兰州大学

学位级别：硕士

Operating systems abstract, multiplex and protect the physical resources of multicore processor computing platforms, and provide resource access interfaces for applications. The abstract interfaces of traditional operating systems are over generalized and high-level resource abstract hides hardware information, which limit the performance, functionality and flexibility of applications. In this thesis, Exokernel architecture is utilized to provide more flexible and efficient interfaces. Exokernel separates resource management from protection, which makes the kernel protects resources and non-privileged applications manage resources. In Exokernel, applications are more flexible and efficient to control resources. The work presented in this thesis is to implement a prototype of Exokernel operating system in single core platform, and then expand it to multicore platforms.The functional components of the single-core prototype include system initialization, memory management, process management and inter-process communication. The components are implemented and validated by step-by-step iteration. Page self-mapping is utilized to safely access page directory entries and page table entries in order to create sub-process in user space. The interrupt handling for page fault in user space is more flexible and secure than the traditional. The more flexible inter-process communication is enabled by message mechanism in user space.To expand the single-core prototype to multicore, this thesis implements the initialization of multicore, including the hard coded page directory and page table to enable paging in each core, and adding process status to avoid one process running in several cores, adopting Big Kernel Lock (BKL) to implement exclusive running of kernel codes in several cores. Finally, there is validation for the functional correctness of Exokernel operating system prototype in multicore platforms.

关键词： multicore processor Multikernel Operating System ExokernelArchitecture Library Operating System

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