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MIMS:Towards a Message Interface Based memory system

Journal of Computer Science & Technology 2014年第2期29卷 255-272页

作者：陈荔城陈明宇阮元黄永兵崔泽汉卢天越包云岗 State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences University of Chinese Academy of Sciences

The decades-old synchronous memory bus interface has restricted many innovations in the memory system, which is facing various challenges （or walls） in the era of multi-core and big data. In this paper, we argue that a message- based interface should be adopted to replace the traditional bus-based interface in the memory system. A novel message interface based memory system called MIMS is proposed. The key innovation of MIMS is that processors communicate with the memory system through a universal and flexible message packet interface. Each message packet is allowed to encapsulate multiple memory requests （or commands） and additional semantic information. The memory system is more intelligent and active by equipping with a local buffer scheduler, which is responsible for processing packets, scheduling memory requests, preparing responses, and executing specific commands with the help of semantic information. Under the MIMS framework, many previous innovations on memory architecture as well as new optimization opportunities such as address compression and continuous requests combination can be naturally incorporated. The experimental results on a 16-core cycle-detailed simulation system show that： with accurate granularity message, MIMS can improve system performance by 53.21% and reduce energy delay product （EDP） by 55.90%. Furthermore, it can improve effective bandwidth utilization by 62.42% and reduce memory access latency by 51% on average.

关键词： message interface memory system asynchronous granularity semantic information

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A Survey of Phase Change memory systems

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Journal of Computer Science & Technology 2015年第1期30卷 121-144页

作者：夏飞蒋德钧熊劲孙凝晖 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100049 China

As the scaling of applications increases, the demand of main memory capacity increases in order to serve large working set. It is difficult for DRAM （dynamic random access memory） based memory system to satisfy the memory capacity requirement due to its limited scalability and high energy consumption. Compared to DRAM, PCM （phase change memory） has better scalability, lower energy leakage, and non-volatility. PCM memory systems have become a hot topic of academic and industrial research. However, PCM technology has the following three drawbacks： long write latency, limited write endurance, and high write energy, which raises challenges to its adoption in practice. This paper surveys architectural research work to optimize PCM memory systems. First, this paper introduces the background of PCM. Then, it surveys research efforts on PCM memory systems in performance optimization, lifetime improving, and energy saving in detail, respectively. This paper also compares and summarizes these techniques from multiple dimensions. Finally, it concludes these optimization techniques and discusses possible research directions of PCM memory systems in future.

关键词： phase change memory memory system performance lifetime energy

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RBC:A memory Architecture for Improved Performance and Energy Efficiency

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Tsinghua Science and Technology 2021年第3期26卷 347-360页

作者： Wenjie Liu Ke Zhou Ping Huang Tianming Yang Xubin He Department of Computer and Information Sciences Temple UniversityPhiladelphiaPA 19122USA Wuhan National Laboratory of Optoelectronics(WNLO) Huazhong University of Science and TechnologyWuhan 430074China Huanghuai University Zhumadian 463000China

DRAM-based memory suffers from increasing row buffer conflicts,which causes significant performance degradation and power *** memory capacity increases,the overheads of the row buffer conflict are increasingly worse as increasing bitline length,which results in high row activation and precharge *** this work,we propose a practical approach called Row Buffer Cache(RBC)to mitigate row buffer conflict overheads *** the core of our proposed RBC architecture,the rows with good spatial locality are cached and protected,which are exempted from being interrupted by the accesses for rows with poor *** an RBC architecture significantly reduces the overheads of performance and energy caused by row activation and precharge,and thus improves overall system performance and energy *** evaluate RBC architecture using SPEC CPU2006 on a DDR4 memory compared to a commodity baseline memory *** show that RBC improves the overall performance by up to 2:24(16:1%on average)and reduces the memory energy by up to 68:2%(23:6%on average)for single-core *** multi-core simulations,RBC increases the overall performance by up to1:55(17%on average)and reduces memory energy consumption by up to 35:4%(21:3%on average).

关键词： memory system Dynamic Random Access memory(DRAM) row buffer conflict

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Toward multi-programmed workloads with different memory footprints: a self-adaptive last level cache scheduling scheme

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Science China(Information Sciences) 2018年第1期61卷 136-149页

作者： Jingyu ZHANG Minyi GUO Chentao WU Yuanyi CHEN Department of Computer Science and Engineering Shanghai Jiao Tong University

With the emerging of 3 D-stacking technology, the dynamic random-access memory(DRAM)can be stacked on chips to architect the DRAM last level cache(LLC). Compared with static randomaccess memory(SRAM), DRAM is larger but slower. In the existing research papers, a lot of work has been devoted to improving the workload performance using SRAM and stacked DRAM together, ranging from SRAM structure improvement, to optimizing cache tag and data access. Instead, little attention has been paid to designing an LLC scheduling scheme for multi-programmed workloads with different memory footprints. Motivated by this, we propose a self-adaptive LLC scheduling scheme, which allows us to utilize SRAM and 3 D-stacked DRAM efficiently, achieving better workload performance. This scheduling scheme employs(1) an evaluation unit, which is used to probe and evaluate the cache information during the process of programs being executed; and(2) an implementation unit, which is used to self-adaptively choose SRAM or DRAM. To make the scheduling scheme work correctly, we develop a data migration policy. We conduct extensive experiments to evaluate the performance of our proposed scheme. Experimental results show that our method can improve the multi-programmed workload performance by up to 30% compared with the state-of-the-art methods.

关键词： 3D-stacking technology cache architecture cache scheduling multi-programmed workloads memory system performance optimization

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