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GShuttle:Optimizing memory access Efficiency for Graph Convolu-tional Neural Network Accelerators

Journal of Computer Science & Technology 2023年第1期38卷 115-127页

作者：李家军王可郑皓 Ahmed Louri School of Astronautics Beihang UniversityBeijing 100191China Department of Electrical and Computer Engineering University of North Carolina at CharlotteCharlotteNC 28223 U.S.A. Department of Electrical and Computer Engineering University of Central FloridaOrlandoFL 32816U.S.A. Department of Electrical and Computer Engineering George Washington UniversityWashingtonDC 20052U.S.A.

Graph convolutional neural networks(GCNs)have emerged as an effective approach to extending deep learning for graph data analytics,but they are computationally challenging given the irregular graphs and the large num-ber of nodes in a *** involve chain sparse-dense matrix multiplications with six loops,which results in a large de-sign space for GCN *** work on GCN acceleration either employs limited loop optimization techniques,or determines the design variables based on random sampling,which can hardly exploit data reuse efficiently,thus degrading system *** overcome this limitation,this paper proposes GShuttle,a GCN acceleration scheme that maximizes memory access efficiency to achieve high performance and energy *** systematically explores loop opti-mization techniques for GCN acceleration,and quantitatively analyzes the design objectives(e.g.,required DRAM access-es and SRAM accesses)by analytical calculation based on multiple design *** further employs two ap-proaches,pruned search space sweeping and greedy search,to find the optimal design variables under certain design *** demonstrated the efficacy of GShuttle by evaluation on five widely used graph *** experimental simulations show that GShuttle reduces the number of DRAM accesses by a factor of 1.5 and saves energy by a factor of 1.7 compared with the state-of-the-art approaches.

关键词： graph convolutional neural network memory access neural network accelerator

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Auxiliary stream for optimizing memory access of video decoders

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Science China(Information Sciences) 2014年第1期57卷 41-50页

作者： LIU ShaoLi LI Ling CHEN YunJi HU WeiWu Institute of Computing Technology Chinese Academy of Sciences

Due to the ever increasing resolution and frame rate of mainstream video sequences,memory access has become the main performance bottleneck of video *** reduce the required of-chip memory,many decoders employ on-chip ***,they cannot distinguish whether a data block is reusable due to the lack of the information of undecoded Macro Blocks(MBs),thus often evicting reusable data from the cache and preserving non-reusable data in the cache,which will lead to a waste of of-chip memory *** this paper,we manage to make full use of cache from a novel perspective,i.e.,auxiliary *** speaking,since the memory access behavior of video decoding is determined in video encoding,the encoder can pack the memory access behaviors of video decoding as auxiliary bitstream,which can inform the decoder whether a data block will be reused by future ***,such an auxiliary stream can enable optimal management of *** efectively reduce the size of auxiliary bitstream,we propose an Auxiliary Prior Information Coding(APIC)method complying with the current video *** future video standards,we introduce a Super Block scan Order(SBO)for MB organization to further reduce the bitrate overhead of auxiliary *** above ideas are evaluated on a number of representative video *** additional prior information can reduce the required of-chip memory bandwidth for motion compensation by over 35%(for a 60 kB cache),while only causing less than 2.3%bitrate increase for high definition(HD)videos.

关键词： video decoding video coding memory access motion compensation auxiliary information

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Characterization of memory access in Deep Learning and Its Implications in memory Management

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Computers, Materials & Continua 2023年第7期76卷 607-629页

作者： Jeongha Lee Hyokyung Bahn Institute of Artificial Intelligence and Software Ewha UniversitySeoul03760Korea Department of Computer Science and Engineering Ewha UniversitySeoul03760Korea

Due to the recent trend of software intelligence in the Fourth Industrial Revolution,deep learning has become a mainstream workload for modern computer *** the data size of deep learning increasingly grows,managing the limited memory capacity efficiently for deep learning workloads becomes *** this paper,we analyze memory accesses in deep learning workloads and find out some unique characteristics differentiated from traditional ***,when comparing instruction and data accesses,data access accounts for 96%–99%of total memory accesses in deep learning workloads,which is quite different from traditional ***,when comparing read and write accesses,write access dominates,accounting for 64%–80%of total memory ***,although write access makes up the majority of memory accesses,it shows a low access bias of 0.3 in the Zipf ***,in predicting re-access,recency is important in read access,but frequency provides more accurate information in write *** on these observations,we introduce a Non-Volatile Random access memory(NVRAM)-accelerated memory architecture for deep learning workloads,and present a new memory management policy for this *** considering the memory access characteristics of deep learning workloads,the proposed policy improves memory performance by 64.3%on average compared to the CLOCK policy.

关键词： memory access deep learning machine learning memory access memory management CLOCK

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Design and Implementation of memory access Fast Switching Structure in Cluster-Based Reconfigurable Array Processor

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Journal of Beijing Institute of Technology 2017年第4期26卷 494-504页

作者： Rui Shan Lin Jiang Junyong Deng Xueting Li Xubang Shen School of Micro-electronics Xidian University Xi' an 710071 China School of Electronic Engineering Xi'an University of Posts and Telecommunication Xi'an 710121 China School of Computer Science & Technology Xi' an University of Posts and Telecommunication Xi' an 710121 China

memory access fast switching structures in cluster are studied,and three kinds of fast switching structures（ FS,LR2 SS,and LAPS） are proposed. A mixed simulation test bench is constructed and used for statistic of data access delay among these three structures in various cases. Finally these structures are realized on Xilinx FPGA development board and DCT,FFT,SAD,IME,FME,and de-blocking filtering algorithms are mapped onto the structures. Compared with available architectures,our proposed structures have lower data access delay and lower area.

关键词： array processor distributed memory memory access switching structure

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