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design of low-power Data Logger of Deep Sea for Long-Term Field Observation

China Ocean Engineering 2009年第1期23卷 133-144页

作者：赵伟陈鹰杨灿军曹建伟顾临怡 The State Key Laboratory of Fluid power Transmission and Control Zhejiang University

This paper describes the implementation of a data logger for the real-time in-situ monitoring of hydrothermal systems. A compact mechanical structure ensures the security and reliability of data logger when used under deep sea. The data logger is a battery powered instrument, which can connect chemical sensors （pH electrode, H2S electrode, H2 electrode） and temperature sensors. In order to achieve major energy savings, dynamic power management is implemented in hardware design and software design. The working current of the data logger in idle mode and active mode is 15 μA and 1.44 mA respectively, which greatly extends the working time of battery. The data logger has been successftdly tested in the first Sino-American Cooperative Deep Submergence Project from August 13 to September 3, 2005.

关键词： data logger low-power design deep sea long-term monitoring

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Toward the Optimal Configuration of Dynamic Voltage Scaling Points in Real-Time Applications

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Journal of Computer Science & Technology 2006年第6期21卷 893-900页

作者：易会战杨学军 School of Computer Science National University of Defense Technology Changsha 410073 P.R. China

In real-time applications, compiler-directed dynamic voltage scaling （DVS） could reduce energy consumption efficiently, where compiler put voltage scaling points in the proper places, and the supply voltage and clock frequency were adjusted to the relationship between the reduced time and the reduced workload. This paper presents the optimal configuration of dynamic voltage scaling points without voltage scaling overhead, which minimizes energy consumption. The conclusion is proved theoretically. Finally, it is confirmed by simulations with equally-spaced voltage scaling configuration.

关键词： low-power design energy-aware systems languages and compilers

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design of Wireless Multi-media Sensor Network for Precision Agriculture

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China Communications 2013年第2期10卷 71-88页

作者：尹首一刘雷波周韧研孙忠富魏少军 Research Center for Mobile Computing Tsinghua University Institute of Microelectronics Tsinghua University Chinese Academy of Agriculture Science

To satisfy the needs of modem pre-cision agriculture, a Precision Agriculture Sensing System （PASS） is designed, which is based on wireless multimedia sensor network. Both hardware and software of PASS are tai-lored for sensing in wide farmland without human supervision. A dedicated single-chip sensor node platform is designed specially for wireless multi-media sensor network. To guarantee the bulky data transmission, a bit-map index reliable data transmission mecha-nism is proposed. And a battery-array switch-ing system is design to power the sensor node to elongate the lifetime. The effectiveness and performance of PASS have been evaluated through comprehensive experiments and large-scale real-life deployment.

关键词： wireless sensor network low-power design reliable transmission pre-cision agriculture

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The Value of a Small Microkernel for Dreamy Memory and the RAMpage Memory Hierarchy

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Journal of Computer Science & Technology 2005年第5期20卷 586-595页

作者： Philip Machanick School of ITEE University of Queensland Brisbane Qld 4072 Australia

This paper explores potential for the RAMpage memory hierarchy to use a microkernel with a small memory footprint, in a specialized cache-speed static RAM （tightly-coupled memory, TCM）. Dreamy memory is DRAM kept in low-power mode, unless referenced. Simulations show that a small microkernel suits RAMpage well, in that it achieves significantly better speed and energy gains than a standard hierarchy from adding TCM. RAMpage, in its best 128KB L2 case, gained 11% speed using TCM, and reduced energy 14%. Equivalent conventional hierarchy gains were under 1%. While 1MB L2 was significantly faster against lower-energy cases for the smaller L2, the larger SRAM＇s energy does not justify the speed gain. Using a 128KB L2 cache in a conventional architecture resulted in a best-case overall run time of 2.58s, compared with the best dreamy mode run time （RAMpage without context switches on misses） of 3.34s, a speed penalty of 29%. Energy in the fastest 128KB L2 case was 2.18J vs. 1.50J, a reduction of 31%. The same RAMpage configuration without dreamy mode took 2.83s as simulated, and used 2.393, an acceptable trade-off （penalty under 10%） for being able to switch easily to a lower-energy mode.

关键词： low-power design main memory virtual memory cache memories microkernels

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