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Research progress on low-power artificial intelligence of things(AIoT) chip design

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Science China(Information Sciences) 2023年第10期66卷 135-151页

作者： Le YE Zhixuan WANG Tianyu JIA Yufei MA Linxiao SHEN Yihan ZHANG Heyi LI Peiyu CHEN Meng WU Ying LIU Yiqi JING Hao ZHANG Ru HUANG School of Integrated Circuits Peking University Advanced Institute of Information Technology of Peking University

An artificial intelligence of things(AIoT) chip is a critical hardware component in edge devices that supports data acquisition and processing in the artificial intelligence(AI) era. In this paper, we introduce the architecture and circuit techniques for AIoT systems as well as the design challenges associated with them.To address the design challenges, we describe our design approaches to improve energy efficiency from the standpoints of system architecture, AI computing, and data acquisition circuits. Meanwhile, we present our most recent research progress and state-of-the-art AIoT chip demonstrations at a prestigious conference. Our design techniques improve power and energy efficiency by orders of magnitude on corresponding state of the arts(SOTA), allowing for an advanced AIoT chip design.

关键词： artificial intelligence (AI) Internet of Things (IoT) low-power chip design random sparse event (RSE)

Anti-Interference low-power Double-Edge Triggered Flip-Flop Based on C-Elements

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Tsinghua Science and Technology 2022年第1期27卷 1-12页

作者： Zhengfeng Huang Xiao Yang Tai Song Haochen Qi Yiming Ouyang Tianming Ni Qi Xu School of Electronic Science and Applied Physics Hefei University of TechnologyHefei 230601China School of Computer and Information Hefei University of TechnologyHefei 230601China School of Electrical Engineering Anhui Polytechnic UniversityWuhu 241000China

When the input signal has been interfered and glitches occur,the power consumption of Double-Edge Triggered Flip-Flops(DETFFs)will significantly increase.To effectively reduce the power consumption,this paper presents an anti-interference low-power DETFF based on C-elements.The improved C-element is used in this DETFF,which effectively blocks the glitches in the input signal,prevents redundant transitions inside the DETFF,and reduces the charge and discharge frequencies of the transistor.The C-element has also added pull-up and pull-down paths,reducing its latency.Compared with other existing DETFFs,the DETFF proposed in this paper only flips once on the clock edge,which greatly reduces the redundant transitions caused by glitches and effectively reduces power consumption.This paper uses HSPICE to simulate the proposed DETFF and other 10 DETFFs.The findings show that compared with the other 10 types of DETFFs,the proposed DETFF has achieved large performance indexes in the total power consumption,total power consumption with glitches,delays,and power delay product.A detailed analysis of variance indicates that the proposed DETFF features less sensitivity to process,voltage,temperature,and Negative Bias Temperature Instability(NBTI)-induced aging variations.

关键词： Double-Edge Triggered Flip-Flop(DETFF) glitch low-power C-element

low-cost low-power UHF RFID tag with on-chip antenna

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Journal of Semiconductors 2009年第7期30卷 137-142页

作者：奚经天闫娜车文毅徐琮辉王肖杨玉庆菅洪彦闵昊 State Key Laboratory of ASIC & System Auto-ID Laboratory Fudan University

This paper presents an EPC Class 1 Generation 2 compatible tag with on-chip antenna implemented in the SMIC 0.18 μm standard CMOS process.The UHF tag chip includes an RF/analog front-end, a digital baseband, and a 640-bit EEPROM memory.The on-chip antenna is optimized based on a novel parasitic-aware model.The rectifier is optimized to achieve a power conversion efficiency up to 40% by applying a self-bias feedback and threshold compensation techniques.A good match between the tag circuits and the on-chip antenna is realized by adjusting the rectifier input impedance.Measurements show that the presented tag can achieve a communication range of 1 cm with 1 W reader output power using a 1 × 1 cm2 single-turn loop reader antenna.

关键词： RFID tag on-chip antenna rectifier low-cost low-power

A low-power triple-mode sigma-delta DAC for reconfigurable(WCDMA/TD-SCDMA/GSM) transmitters

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Journal of Semiconductors 2011年第2期32卷 96-101页

作者：邱东易婷洪志良 State Key Laboratory of ASlC and System Fudan University

A sigma-delta （∑A） DAC with channel filtering for multi-standard wireless transmitters used in the software-defined-radio （SDR） system is presented. The conversion frequency, transfer function of the digital filter and the ∑A modulator, word-length of the IDAC and cut-off frequency of the analog reconstruction filter can be digitally programmed to satisfy specifications of WCDMA, TD-SCDMA and GSM standards. The ∑A DAC fabricated in SMIC 0.13μm CMOS process occupies a die area of 0.72 mm2, while consuming 5.52/4.82/3.04 mW in WCDMA/TD-SCDMA/GSM mode from a single 1.2-V supply voltage. The measured SFDR is 62.8/60.1/ 75.5 dB for WCDMA/TD-SCDMA/GSM mode, respectively.

关键词： ∑A digital-to-analog converter low-power reconfigurable

A low-power time-domain VCO-based ADC in 65 nm CMOS

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Journal of Semiconductors 2014年第10期35卷 140-145页

作者：王陈銮刁盛锡林福江 Department of Electronic Science & Technology University of Science and Technology of China

A low-power, high-FoM （figure of merit）, time-domain VCO （voltage controlled oscillator）-based ADC （analog-to-digital converter） in 65 nm CMOS technology is proposed. An asynchronous sigma-delta modulator （ASDM） is used to convert the voltage input signal to a square wave time signal, where the information is contained in its pulse-width. A time-domain quantizer, which uses VCO to convert voltage to frequency, is adopted, while the XOR （exclusive-OR） gate circuits convert the frequency information to digital representatives. The ASDM does not need an external clock, so there is no quantization noise. At the same time, the ASDM applies a harmonic- distortion-cancellation technique to its transconductance stage, which increases the SNDR （signal to noise and distortion ratio） performance of the ASDM. Since the output of the ASDM is a two-level voltage signal, the VCO＇s V-F （voltage to frequency） conversion curve is always linear. The XOR phase quantizer has an inherent feature of first-order noise-shaping. It puts the ADC＇s low-frequency output noise to high-frequency which is further filtered out by a low-pass filter. The proposed ADC achieves an SNR/SNDR of 54. dB/54.3 dB in the 8 MHz bandwidth, while consuming 2.8 mW. The FoM of the proposed ADC is a 334 fJ/conv-step.

关键词： VCO ADC ASDM PWM （pulse width modulation） nonlinearity low-power

A feedforward compensation design in critical conduction mode boost power factor correction for low-power low total harmonic distortion

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Journal of Semiconductors 2012年第3期33卷 87-93页

作者：李娅妮杨银堂朱樟明强玮 Institute of Microelectronics Xidian University Xi'an Longtium Microelectronics Technology Developing Co. Ltd

For low-power low total harmonic distortion（THD）,based on the CSMC 0.5μm BCD process,a novel boost power factor correction（PFC） converter in critical conduction mode is discussed and analyzed.Feedforward compensation design is introduced in order to increase the PWM duty cycle and supply more conversion energy near the input voltage zero-crossing points,thus regulating the inductor current of the PFC converter and compensating the system loop gain change with ac line voltage.Both theoretical and practical results reveal that the proposed PFC converter with feedforward compensation cell has better power factor and THD performance,and is suitable for low-power low THD design applications.The experimental THD of the boost PFC converter is 4.5%,the start-up current is 54μA,the stable operating current is 3.85 mA,the power factor is 0.998 and the efficiency is 95.2%.

关键词： CRM boost PFC low-power THD feedforward compensation

Mechanisms for non-ideal flow in low-power arc-heated supersonic nozzles

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Acta Mechanica Sinica 2015年第4期31卷 500-511页

作者： Cheng-Kang Wu Wen-Xia Pan Xian Meng Hai-Xing Wang State Key Laboratory of High Temperature Gas Dynamics Institute of Mechanics Chinese Academy of Sciences School of Astronautics Beijing University of Aeronautics and Astronautics

The flow in a low-powered arc gas heater com- bined with a supersonic nozzle of throat diameter less than 1 mm is quite complicated and difficult to describe in quan- titative detail. Experiments on arc-heated supersonic jet thrusters of monatomic gases argon and helium have been carried out and their performance measured. The flow charac- teristics are analyzed with the help of numerical simulation. Results show that the viscous effect is the most important factor causing the large difference between ideal and real performance. A large outer section of the exit flow is slow- moving. This is especially pronounced in helium, where 70 % of the exit area of the nozzle might be in subsonic flow. Fric- tion forces can be much larger than the net thrust, reaching several times higher in helium, resulting in very low efficien- cies. Other factors causing the differences between ideal and real flow include： complex flow in the throat region, electric arc extending to the nozzle expansion section, heat transfer to the inlet gas and from the hot plasma, and environmen- tal pressure in the vacuum chamber. It is recognized that the ordinary concepts of supersonic nozzle flow must be greatly modified when dealing with such complicated situations. The general concepts presented in this paper could be helpful in guiding the design and operation of this equipment.

关键词： Arc-heated supersonic jet low-power Real flow Viscosity effect low Reynolds number

A low-power current self-adjusted VCO using a bottom PMOS current source

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Journal of Semiconductors 2014年第9期35卷 126-130页

作者：盛志雄于峰崎 Department of Integrated Electronics Shenzhen Institutes of Advanced Technology Chinese Academy of Sciences Institute of Microelectronics Chinese Academy of Sciences The Chinese University of Hong Kong University of Chinese Academy of Sciences

This paper presents the design and implementation of a current self-adjusted VCO with low power consumption. In the proposed VCO, a bottom PMOS current source instead of a top one is adopted to decrease the tail noise. A current self-adjusted technique without additional external control signals is taken to ensure the VCO starts up in the whole band while keeping the power consumption relatively low. Meanwhile, the phase noise of the VCO at the low frequency （high Cvar） can be reduced by the technique. The circuit is implemented in 0.18 μm CMOS technology. The proposed VCO exhibits low power consumption of 〈1.6 mW at a 1.5 V supply voltage and a tuning range from 11.79 to 12.53 GHz. The measured phase noise at 1 MHz offset from the frequency 11.79 GHz is-104.7 dBc/Hz, and the corresponding FOM is -184.2 dBc/Hz.

关键词： low-power phase-noise quality factor current self-adjusted technique voltage-controlled oscillator

Architecture design of low-power motion estimation based on DHS-NPDS for H.264/AVC

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Science China(Information Sciences) 2012年第10期55卷 2234-2242页

作者： CHEN YunBi 1,LI ZhengDong 2,GUO Li 1,XIE JinSheng 1 & ZHAO Long 1 1 Department of Electronic Science and Technology,University of Science and Technology of China,Hefei 230027,China 2 Staff room of Electronic and Technology,Chongqing Communication College,Chongqing 400035,China Department of Electronic Science and Technology University of Science and Technology of China Hefei China Staff room of Electronic and Technology Chongqing Communication College Chongqing China

A novel architecture of motion estimation(ME) based on improved normalized partial distortion search is proposed to meet three primary requirements for real-time video encoding,which are low-power,lowbandwidth and high area utilization efficiency.The ME engine supports both normalized partial distortion search and adaptive search window adjustment.The former can reduce the computational complexity of ME to save power and area;the latter can avoid unnecessary accessing the external memory to lower the data bandwidth.The proposed engine has been implemented with UMC 90nm CMOS technology.The implementation results show that,compared with traditional engines,the engine can achieve significant improvements of the hardware efficiency and the power efficiency respectively with a little throughput compromise.

关键词： partial distortion search adaptive search range low-power low-bandwidth pipeline VLSI