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Darwin3: a large-scale neuromorphic chip with a novel ISA and on-chip learning

National Science Review 2024年第5期11卷 29-45页

作者： De Ma Xiaofei Jin Shichun Sun Yitao Li Xundong Wu Youneng Hu Fangchao Yang Huajin Tang Xiaolei Zhu Peng Lin Gang Pan College of Computer Science and Technology Zhejiang University Research Center for Intelligent Computing Hardware Zhejiang Lab The State Key Lab of Brain-Machine Intelligence Zhejiang University MOE Frontier Science Center for Brain Science and Brain-machine Integration Zhejiang University College of Micro-Nano College of Micro-Nano Electronics Zhejiang University

Spiking neural networks(SNNs) are gaining increasing attention for their biological plausibility and potential for improved computational efficiency. To match the high spatial-temporal dynamics in SNNs,neuromorphic chips are highly desired to execute SNNs in hardware-based neuron and synapse circuits directly. This paper presents a large-scale neuromorphic chip named Darwin3 with a novel instruction set architecture, which comprises 10 primary instructions and a few extended instructions. It supports flexible neuron model programming and local learning rule designs. The Darwin3 chip architecture is designed in a mesh of computing nodes with an innovative routing algorithm. We used a compression mechanism to represent synaptic connections, significantly reducing memory usage. The Darwin3 chip supports up to2.35 million neurons, making it the largest of its kind on the neuron scale. The experimental results showed that the code density was improved by up to 28.3× in Darwin3, and that the neuron core fan-in and fan-out were improved by up to 4096× and 3072× by connection compression compared to the physical memory depth. Our Darwin3 chip also provided memory saving between 6.8× and 200.8× when mapping convolutional spiking neural networks onto the chip, demonstrating state-of-the-art performance in accuracy and latency compared to other neuromorphic chips.

关键词： neuromorphic computing spiking neural network instruction set architecture connectivity compression

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UNI-SPEC:An instruction set Description Language

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High Technology Letters 2003年第4期9卷 33-38页

作者：朱德新 Cheng Xu Song Chuanhua Microprocessor Research Center Peking University Beijing 100871 P.R. China

Microprocessor development emphasizes hardware and software co design. Hw/Sw co design is a modern technique aimed at shortening the time to market in designing the real time and embedded systems. Key feature of this approach is simultaneous development of the program tools and the target processor to match software application. An effective co design flow must therefore support automatic software toolkits generation, without loss of optimizing efficiency. This has resulted in a paradigm shift towards a language based design methodology for microprocessor optimization and exploration. This paper proposes a formal grammar, UNI SPEC, which supports the automatic generation of assemblers, to describe the translation rules from assembly to binary. Based on UNI SPEC, it implements two typical applications, i.e., automatically generating the assembler and the test suites.

关键词： formal grammar retargetable assembler generator instruction set architecture

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Single-Cycle Bit Permutations with MOMR Execution

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Journal of Computer Science & Technology 2005年第5期20卷 577-585页

作者：李佩露杨骁史志杰 Department of Electrical Engineering Princeton University Princeton NJ 08544 U.S.A. Department of Computer Science and Engineering University of Connecticut Storrs CT 06269 U.S.A.

Secure computing paradigms impose new architectural challenges for general-purpose processors. Cryptographic processing is needed for secure communications, storage, and computations. We identify two categories of operations in symmetric-key and public-key cryptographic algorithms that are not common in previous general-purpose workloads： advanced bit operations within a word and multi-word operations. We define MOMR （Multiple Operands Multiple Results） execution or datarich execution as a unified solution to both challenges. It allows arbitrary n-bit permutations to be achieved in one or two cycles, rather than O（n） cycles as in existing RISC processors. It also enables significant acceleration of multiword multiplications needed by public-key ciphers. We propose two implementations of MOMR： one employs only hardware changes while the other uses instruction set architecture （ISA） support. We show that MOMR execution leverages available resources in typical multi-issue processors with minimal additional cost. Multi-issue processors enhanced with MOMR units provide additional speedup over standard multi-issue processors with the same datapath. MOMR is a general architectural solution for word-oriented processor architectures to incorporate datarich operations.

关键词： permutation bit permutations cryptography cryptographic acceleration security multi-word operation,datarich execution MOMR instruction set architecture ISA processor high performance secure computing

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