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An FPGA-Based Resource-Saving hardware accelerator for Deep Neural Network

International Journal of Intelligence Science 2021年第2期11卷 57-69页

作者： Han Jia Xuecheng Zou School of Optical and Electronic Information Huazhong University of Science and Technology Wuhan China

With the development of computer vision researches, due to the state-of-the-art performance on image and video processing tasks, deep neural network (DNN) has been widely applied in various applications (autonomous vehicles, weather forecasting, counter-terrorism, surveillance, traffic management, etc.). However, to achieve such performance, DNN models have become increasingly complicated and deeper, and result in heavy computational stress. Thus, it is not sufficient for the general central processing unit (CPU) processors to meet the real-time application requirements. To deal with this bottleneck, research based on hardware acceleration solution for DNN attracts great attention. Specifically, to meet various real-life applications, DNN acceleration solutions mainly focus on issue of hardware acceleration with intense memory and calculation resource. In this paper, a novel resource-saving architecture based on Field Programmable Gate Array (FPGA) is proposed. Due to the novel designed processing element (PE), the proposed architecture achieves good performance with the extremely limited calculating resource. The on-chip buffer allocation helps enhance resource-saving performance on memory. Moreover, the accelerator improves its performance by exploiting the sparsity property of the input feature map. Compared to other state-of-the-art solutions based on FPGA, our architecture achieves good performance, with quite limited resource consumption, thus fully meet the requirement of real-time applications.

关键词： Deep Neural Network Resource-Saving hardware accelerator Data Flow

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Towards High-Performance Graph Processing: From a hardware/Software Co-Design Perspective

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Journal of Computer Science & Technology 2024年第2期39卷 245-266页

作者：廖小飞赵文举金海姚鹏程黄禹王庆刚赵进郑龙张宇邵志远 National Engineering Research Center for Big Data Technology and System School of Computer Science and Technology Huazhong University of Science and TechnologyWuhan 430074China Services Computing Technology and System Laboratory School of Computer Science and Technology Huazhong University of Science and TechnologyWuhan 430074China Cluster and Grid Computing Laboratory School of Computer Science and TechnologyHuazhong University of Science and TechnologyWuhan 430074China Zhejiang Lab Hangzhou 311121China

Graph processing has been widely used in many scenarios,from scientific computing to artificial *** processing exhibits irregular computational parallelism and random memory accesses,unlike traditional ***,running graph processing workloads on conventional architectures(e.g.,CPUs and GPUs)often shows a significantly low compute-memory ratio with few performance benefits,which can be,in many cases,even slower than a specialized single-thread graph *** domain-specific hardware designs are essential for graph processing,it is still challenging to transform the hardware capability to performance boost without coupled software *** article presents a graph processing ecosystem from hardware to *** start by introducing a series of hardware accelerators as the foundation of this ***,the codesigned parallel graph systems and their distributed techniques are presented to support graph ***,we introduce our efforts on novel graph applications and hardware *** results show that various graph applications can be efficiently accelerated in this graph processing ecosystem.

关键词： graph processing hardware accelerator software system high performance ecosystem

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A Survey on Graph Neural Network Acceleration: A hardware Perspective

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Chinese Journal of Electronics 2024年第3期33卷 601-622页

作者： Shi CHEN Jingyu LIU Li SHEN School of Computer National University of Defense Technology Key Laboratory of Advanced Microprocessor Chips and Systems

Graph neural networks(GNNs) have emerged as powerful approaches to learn knowledge about graphs and *** rapid employment of GNNs poses requirements for processing *** to incompatibility of general platforms,dedicated hardware devices and platforms are developed to efficiently accelerate training and inference of *** conduct a survey on hardware acceleration for *** first include and introduce recent advances of the domain,and then provide a methodology of categorization to classify existing works into three ***,we discuss optimization techniques adopted at different *** finally we propose suggestions on future directions to facilitate further works.

关键词： Graph neural networks Deep learning acceleration Domain-specific architecture hardware accelerator MODEL

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hardware Acceleration for SLAM in Mobile Systems

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Journal of Computer Science & Technology 2023年第6期38卷 1300-1322页

作者：樊哲郝一帆支天郭崎杜子东 State Key Laboratory of Processors Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China School of Computer Science and Technology University of Chinese Academy of SciencesBeijing 100049China Cambricon Technologies Beijing 100191China

The emerging mobile robot industry has spurred a flurry of interest in solving the simultaneous localization and mapping(SLAM)***,existing SLAM platforms have difficulty in meeting the real-time and low-pow-er requirements imposed by mobile *** specialized hardware is promising with regard to achieving high per-formance and lowering the power,designing an efficient accelerator for SLAM is severely hindered by a wide variety of SLAM *** on our detailed analysis of representative SLAM algorithms,we observe that SLAM algorithms advance two challenges for designing efficient hardware accelerators:the large number of computational primitives and ir-regular control *** address these two challenges,we propose a hardware accelerator that features composable com-putation units classified as the matrix,vector,scalar,and control *** addition,we design a hierarchical instruction set for coping with a broad range of SLAM algorithms with irregular control *** results show that,com-pared against an Intel x86 processor,on average,our accelerator with the area of 7.41 mm^(2) achieves 10.52x and 112.62x better performance and energy savings,respectively,across different *** against a more energy-efficient ARM Cortex processor,our accelerator still achieves 33.03x and 62.64x better performance and energy savings,respec-tively.

关键词： hardware accelerator instruction set mobile system simultaneous localization and mapping(SLAM)algorithm

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