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Efficient fault Tree Analysis of Complex fault tolerant Multiple-Phased systems

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Tsinghua Science and Technology 2007年第S1期12卷 122-127页

作者：莫毓昌刘宏伟杨孝宗 Department of Computer Science and Technology Harbin Institute of Technology

fault tolerant multiple phased systems (FTMPS), i.e., systems whose critical components are independently replicated and whose operational life can be partitioned in a set of disjoint periods, are called 'phases'. Because of their deployment in critical applications, their reliability analysis is a task of primary relevance to validate the designs. fault tree analysis based on binary decision diagram (BDD) is one of the most commonly used techniques for FTMPS reliability analysis. To utilize the technique the fault tree structure of FTMPS needs to be converted into the corresponding BDD format. Our research work shows that the system BDD generation algorithms presented in the literature are too inefficient to be used for industrial complex FTPMS because of the problems, such as variable ordering and combination of large BDDs. This paper presents a more efficient approach consisting of a flatting pre-processing technique, a proved efficient ordering heuristic and a bottom-up generation algorithm. The approach tries to combine share-variable BDDs by complex combination operation firstly and then combine no-share-variable BDDs using simple combination operation, thus to alvoid the intensive computations caused by large BDD combination operations. An example FTMPS is analyzed to illustrate the advantages of our approach.

关键词： fault tolerant system reliability analysis fault tree analysis multiple-phased system variable or-dering heuristic

HYBRID REDUNDANCY APPROACH TO INCREASE THE RELIABILITY OF FPGA BASED SPEED CONTROLLER CORE FOR HIGH SPEED TRAIN

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Journal of Electronics(China) 2014年第3期31卷 256-266页

作者： Omid Akbari Galashi Karim Mohammadi Reza Omidi Gosheblagh Department of Electrical Engineering Iran University of Science and Technology (IUST)NarmakTehran 16846-13114 Iran

With the progress of the railway technology, the railway transportation is becoming more efficient, intelligent and faster. High speed trains, as a major part of the railway transportation, are engaged with passenger's safety, and therefore the reliability issue is very important in such vital systems. In this paper, a dependable speed controller core based on FPGA has been developed for high speed trains. To improve the reliability and mitigate single upset faults on basic speed controller, this paper proposes a new effective method which is based on hardware redundancy. In the proposed Hybrid Dual Duplex Redundancy(HDDR) method, the original controller is quadruplicated and correct values are voted through the comparator and error detection unit. We have analyzed the proposed system with Reliability, Availability, Mean time to failure and Security(RAMS) theory in order to evaluate the effectiveness of proposed scheme. Theoretical analysis shows that the Mean Time To Failure(MTTF) of the proposed system is 2.5 times better than the traditional Triple Modular Redundancy(TMR). Furthermore, the fault injection experimental results reveal that the capability of tolerating Single Event Upsets(SEUs) in the proposed method increases up to 7.5 times with respect to a regular speed controller.

关键词： Field Programmable Gate Arrays (FPGAs) Hybrid Dual Duplex Redundancy (HDDR) fault tolerant system Reliability High speed railway

fault-tolerant Bit-Parallel Multiplier for Polynomial Basis of GF（2^m）

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Journal of Electronic Science and Technology of China 2009年第4期7卷 343-347页

作者： Chiou-Yng Lee Pramod Kumar Meher Chia-Chen Fan Computer Information and Network Engineering Lunghwa University of Science and Technology Department of Communication systems Institute for Infocomm Research

Novel fault-tolerant architectures for bit-parallel polynomial basis multiplier over GF（2^m）, which can correct the erroneous outputs using linear code, are presented. A parity prediction circuit based on the code generator polynomial that leads lower space overhead has been designed. For bit-parallel architectures, the Moreover, there is incorporation of space overhead only marginal time error-correction is about 11%. overhead due to capability that amounts to 3.5% in case of the bit-parallel multiplier. Unlike the existing concurrent error correction （CEC） multipliers or triple modular redundancy （TMR） techniques for single error correction, the proposed architectures have multiple error-correcting capabilities.

关键词： fault tolerant system finite field parity prediction.