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Techniques for Design and Implementation of an FPGA-Specific Physical Unclonable Function

Journal of Computer Science & Technology 2016年第1期31卷 124-136页

作者： Ji-Liang Zhang Qiang Wu Yi-Peng Ding Yong-Qiang Lv Qiang Zhou Zhi-Hua Xia Xing-Ming Sun Xing-Wei Wang Software College Northeastern University Shenyang 110819 China College of Information Science and Engineering Hunan University Changsha 410082 China School of Physics and Electronics Central South University Changsha 410083 China Research Institute of Information Technology Tsinghua University Beijing 100084 China School of Computer and Software Nanjing University of Information Science and Technology Nanjing 210044 China

Physical unclonable function （PUF） makes use of the uncontrollable process variations during the production of IC to generate a unique signature for each IC. It has a wide application in security such as FPGA intellectual property （IP） protection, key generation and digital rights management. Ring oscillator （RO） PUF and Arbiter PUF are the most popular PUFs, but they are not specially designed for FPGA. RO PUF incurs high resource overhead while obtaining less challenge-response pairs, and requires ＂hard macros＂ to implement on FPGAs. The arbiter PUF brings low resource overhead, but its structure has big bias when it is mapped on FPGAs. Anderson PUF can address these weaknesses of current Arbiter and RO PUFs implemented on FPGAs. However, it cannot be directly implemented on the new generation 28 nm FPGAs. In order to address these problems, this paper designs and implements a delay-based PUF that uses two LUTs in an SLICEM to implement two 16-bit shift registers of the PUF, 2-to-1 multiplexers in the carry chain to implement the multiplexers of the PUF, and any one of the 8 flip-flops to latch 1-bit PUF signatures. The proposed delay-based PUF is completely realized on 28 nm commercial FPGAs, and the experimental results show its high uniqueness, reliability and reconfigurability. Moreover, we test the impact of aging on it, and the results show that the effect of aging on the proposed PUF is insignificant, with only 6% bit-flips. Finally, the prospects of the proposed PUF in the FPGA binding and volatile key generation are discussed.

关键词： physical unclonable function (PUF) FPGA intellectual property protection fabrication variation hardware security

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