In this paper, we investigated the electrical properties of the Metal-oxide-semiconductor gate stack of Ti/AlO/In P under different annealing conditions. A minimum interface trap density of 3×10cmeVis obtained withou...
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In this paper, we investigated the electrical properties of the Metal-oxide-semiconductor gate stack of Ti/AlO/In P under different annealing conditions. A minimum interface trap density of 3×10cmeVis obtained without postmetallization annealing ***, utilizing Ti/AlO/In P MOS gate stack,we fabricated ultra-thin body buried In0.35 Ga0.65 As channel MOSFETs on Si substrates with optimized on/off trade-off. The 200 nm gate length device with extremely low off-current of 0.6 n A/μm, and on-off ratio of 3.3×10, is demonstrated by employing buried low indium(InGaAs) channel with In P barrier/spacer device structure, giving strong potential for future highperformance and low-power applications.
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