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Influences of different structures on the characteristics of H_2O-based and O_3-based La_xAl_yO films deposited by atomic layer deposition

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Chinese Physics B 2016年第5期25卷 434-440页

作者：费晨曦刘红侠汪星赵冬冬王树龙陈树鹏 Key Laboratory for Wide-Band Gap Semiconductor Materials and Devices of Education School of Microelectronics Xidian University

H_2O-based and O_3-based La_xAl_yO nanolaminate films were deposited on Si substrates by atomic layer deposition（ALD）. Structures and performances of the films were changed by different barrier layers. The effects of different structures on the electrical characteristics and physical properties of the La_xAl_yO films were studied. Chemical bonds in the La_xAl_yO films grown with different structures and different oxidants were also investigated with x-ray photoelectron spectroscopy（XPS）. The preliminary testing results indicate that the La_xAl_yO films with different structures and different oxidants show different characteristics, including dielectric constant, equivalent oxide thickness（EOT）, electrical properties, and stability.

关键词： atomic layer deposition oxidant dielectric constant equivalent oxide thickness

Combining a multi deposition multi annealing technique with a scavenging(Ti) to improve the high-k/metal gate stack performance for a gate-last process

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Journal of Semiconductors 2014年第10期35卷 182-186页

作者：张淑祥杨红唐波唐兆云徐烨峰许静闫江 Institute of Microelectronics Chinese Academy of Sciences

ALD HfO2 films fabricated by a novel multi deposition multi annealing （MDMA） technique are inves- tigated, we have included samples both with and without a Ti scavenging layer. As compared to the reference gate stack treated by conventional one-time deposition and annealing （D＆A）, devices receiving MDMA show a signif- icant reduction in leakage current. Meanwhile, EOT growth is effectively controlled by the Ti scavenging layer. This improvement strongly correlates with the cycle number of D＆A （while keeping the total annealing time and total dielectrics thickness the same）. Transmission electron microscope and energy-dispersive X-ray spectroscopy analysis suggests that oxygen incorporation into both the high-k film and the interfacial layer is likely to be re- sponsible for the improvement of the device. This novel MDMA is promising for the development of gate stack technology in a gate last integration scheme.

关键词： postdeposition annealing scavenging oxygen vacancy equivalent oxide thickness metal gate high-k

Effect of Er ion implantation on the physical and electrical properties of TiN/HfO_2 gate stacks on Si substrate

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Science China(Physics,Mechanics & Astronomy) 2013年第7期56卷 1384-1388页

作者： ZHAO Mei LIANG RenRong WANG Jing XU Jun Tsinghua National Laboratory for Information Science and Technology Institute of MicroelectronicsTsinghua University

In this paper, we report the fabrication, electrical and physical characteristics of TiN/HfO2/Si MOS capacitors with erbium （Er） ion implantation. It is demonstrated that the fiat band voltage can be reduced by 0.4 V due to the formation of Er oxide. Moreover, it is observed that the equivalent oxide thickness is thinned down by 0.5 nm because the thickness of interfacial layer is significantly reduced, which is thought to be attributed to the strong binding capability of the implanted Er atoms with oxygen atoms. In addition, cross-sectional transmission electron microscopy experiment shows that the HfO2 layer with Er ion implantation is still amorphous after annealing at a high temperature. This Er ion implantation technique has the potential to be implemented as a band edge metal gate solution for NMOS without a capping layer, and may also satisfy the demand of the EOT reduction in 32 nm technology node.

关键词： erbium ion implantation high-k/metal-gate equivalent oxide thickness fiat band voltage interfacial layer crystallization

探索Bi_(2)SeO_(5)的高介电性能:从块体到双层和单层

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Science China Materials 2024年第3期67卷 906-913页

作者：董欣月何育彧管乐祝元昊吴金雄付会霞颜丙海 Tianjin Key Lab for Rare Earth Materials and Applications Center for Rare Earth and Inorganic Functional MaterialsSmart Sensor Interdisciplinary Science CenterSchool of Materials Science and EngineeringNankai UniversityTianjin 300350China Center of Quantum Materials and Devices College of PhysicsChongqing UniversityChongqing 401331China Chongqing Key Laboratory for Strongly Coupled Physics Chongqing UniversityChongqing 401331China Department of Condensed Matter Physics Weizmann Institute of ScienceRehovot 7610001Israel

Bi_(2)SeO_(5)是一种具有优异电绝缘性能的范德华(vdW)层状介电材料,引起了极大关注.然而,目前关于Bi_(2)SeO_(5)的研究主要停留在实验层面,仍然缺乏对其原子级薄膜的介电性能的相关理论认识.本文通过第一性原理计算确定了Bi_(2)SeO_(5... 详细信息

Bi_(2)SeO_(5)是一种具有优异电绝缘性能的范德华(vdW)层状介电材料,引起了极大关注.然而,目前关于Bi_(2)SeO_(5)的研究主要停留在实验层面,仍然缺乏对其原子级薄膜的介电性能的相关理论认识.本文通过第一性原理计算确定了Bi_(2)SeO_(5)的介电性能,发现其块体、双层和单层均具有超高平均介电常数(εr>20).研究表明,单层Bi_(2)SeO_(5)与双层Bi_(2)O_(2)Se之间的导带和价带能量偏移量均大于1 eV,表明单层Bi_(2)SeO_(5)依然可作为原子薄Bi_(2)O_(2)Se的良好介电层.此外,不同于h-BN或其他2D vdW绝缘体,Bi_(2)SeO_(5)的εr由其离子部分主导,且随着厚度的减小几乎保持不变.计算发现,单层Bi_(2)SeO_(5)的等效氧化层厚度可薄至0.3 n m,且单层Bi_(2)SeO_(5)在拉伸或压缩应变达到6%时均能保持高介电常数,这极大地促进了它与各种二维半导体的集成.本工作证明单层Bi_(2)SeO_(5)可以作为高性能二维电子器件良好的封装和介电层.

关键词： Bi_(2)SeO_(5) high-κ equivalent oxide thickness dielectric constant van der Waals first-principles calculations

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A High Performance Sub-100nm Nitride/Oxynitride Stack Gate Dielectric CMOS Device with Refractory W/TiN Metal Gates

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Journal of Semiconductors 2006年第3期27卷 448-453页

作者：钟兴华周华杰林钢徐秋霞中国科学院微电子研究所北京100029

By complementing the equivalent oxide thickness （EOT） of a 1.7nm nitride/oxynitride （N/O） stack gate dielectric （EOT- 1.7nm） with a W/TiN metal gate electrode,metal gate CMOS devices with sub-100nm gate length are fabricated in China for the first time. The key technologies adopted to restrain SCE and to improve drive ability include a 1.7nm N/O stack gate dielectric, non-CMP planarization technology, a T-type refractory W/TiN metal stack gate electrode, and a novel super steep retrograde channel doping using heavy ion implantation and a double sidewall scheme. Using these optimized key technologies, high performance 95nm metal gate CMOS devices with excellent SCE and good driving ability are fabricated. Under power supply voltages of VDS ± 1.5V and VGS± 1.8V,drive currents of 679μA/μm for nMOS and - 327μA/μm for pMOS are obtained. A subthreshold slope of 84.46mV/dec, DIBL of 34.76mV/V, and Vth of 0.26V for nMOS, and a subthreshold slope of 107.4mV/dec,DIBL of 54.46mV/V, and Vth of 0.27V for pMOS are achieved. These results show that the combined technology has indeed thoroughly eliminated the boron penetration phenomenon and polysilicon depletion effect ,effectively reduced gate tunneling leakage, and improved device reliability.

关键词： equivalent oxide thickness nitride/oxynitride gate dielectric stack W/TiN metal gate non-CMP planarization

Electrical Properties of Ultra Thin Nitride/Oxynitride Stack Dielectrics pMOS Capacitor with Refractory Metal Gate

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Journal of Semiconductors 2005年第4期26卷 651-655页

作者：钟兴华吴峻峰杨建军徐秋霞中国科学院微电子研究所北京100029

Electrical properties of high quality ultra thin nitride/oxynitride(N/O)stack dielectrics pMOS capacitor with refractory metal gate electrode are investigated,and ultra thin (<2 nm) N/O stack gate dielectrics with significant low leakage current and high resistance to boron penetration are *** results show that the stack gate dielectric of nitride/oxynitride combined with improved sputtered tungsten/titanium nitride (W/TiN) gate electrode is one of the candidates for deep sub-micron metal gate CMOS devices.

关键词： equivalent oxide thickness nitride/oxynitride gate dielectric stack high k boron-penetration metal gate