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Shared Cache Based on Content Addressable Memory in a Multi-Core Architecture

Computers, Materials & Continua 2023年第3期74卷 4951-4963页

作者： Allam Abumwais Mahmoud Obaid Computer Systems Engineering Arab American UniversityJenin240Palestine

Modern shared-memory multi-core processors typically have shared Level 2(L2)or Level 3(L3)*** bottlenecks and replacement strategies are the main problems of such architectures,where multiple cores try to access the shared cache *** main problem in improving memory performance is the shared cache architecture and cache *** paper documents the implementation of a dual-port Content Addressable Memory(DPcam)and a modified Near-Far Access Replacement Algorithm(NFRA),which was previously proposed as a shared L2 cache layer in a multi-core *** Performance Evaluation Corporation(SPEC)Central Processing Unit(CPU)2006 benchmark workloads are used to evaluate the benefit of the shared L2 cache *** show improved performance of the multicore processor’s DPcam and NFRA algorithms,corresponding to a higher number of concurrent accesses to shared *** new architecture significantly increases system throughput and records performance improvements of up to 8.7%on various types of SPEC 2006 *** miss rate is also improved by about 13%,with some exceptions in the sphinx3 and bzip2 *** results could open a new window for solving the long-standing problems with shared cache in multi-core processors.

关键词： Multi-core processor shared cache content addressable memory dual port cam replacement algorithm benchmark program

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dual-port Content Addressable Memory for Cache Memory Applications

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Computers, Materials & Continua 2022年第3期70卷 4583-4597页

作者： Allam Abumwais Adil Amirjanov Kaan Uyar Mujahed Eleyat Department of Computer Engineering Near East UniversityNicosiaN.Cyprus via Mersin-10Turkey Computer Systems Engineering Arab American UniversityJenin240Palestine

Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory *** paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual port content addressable memory(DPcam).In addition,it proposes a new replacement algorithm based on hardware which is called a near-far access replacement algorithm(NFRA)to reduce the cost overhead of the cache controller and improve the cache access *** experimental results indicated that the latency for write and read operations are significantly less in comparison with a set-associative cache ***,it was shown that a latency of a read operation is nearly constant regardless of the size of ***,an estimation of the power dissipation showed that DPcam consumes about 7%greater than a set-associative cache memory of the same *** results encourage for embedding DPcam within the multicore processors as a small shared cache memory.

关键词： Multicore system content addressable memory dual port cam cache controller set-associative cache power dissipation

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