检索结果-南通市图书馆

Designing current–strain-assisted superconductor–ferromagnet multi-bit memories

Chinese Physics B 2022年第11期31卷 619-625页

作者： Hasnain Mehdi Jafri Jing Wang Xiao-Ming Shi De-Shan Liang Hou-Bing Huang School of Materials Science&Engineering Beijing Institute of TechnologyBeijing 100081China Advanced Research Institute of Multidisciplinary Science Beijing Institute of TechnologyBeijing 100081China

Current superconducting memory devices lack the basic quality of high memory density for practical memories,mainly due to the size limitations of superconducting quantum interference ***,we propose a superconductor–ferromagnet bilayer device with strain-pulse-assisted multi-bit ladder-type memory,by using strain-engineered ferromagnet domain structure to control carrier concentration in the superconductor,which is simulated by coupled Landau–Lifshitz–Gilbert and Ginzburg–Landau ***-and strain-pulses are observed to deterministically control the resistivity of superconductor for one and two-bit device *** average carrier concentration of superconductor is observed to have multiple metastable states that can be controllably switched using current-pulse and strain-pulse to determine multiple resistivity *** findings confirm the eligibility of superconductor–ferromagnet bilayers to be used as ladder-type multibit memories and open a new way for further theoretical and experimental investigations of the cryogenic memories.

关键词： superconductor-ferromagnet bilayer cryogenic memories superconducting memories vortex memories

来源：

维普期刊数据库

同方期刊数据库评论

在线全文

学校读者我要写书评

暂无评论

The future is frozen:cryogenic CMOS for high-performance computing

引用

Chip 2024年第1期3卷 43-54页

作者： R.Saligram A.Raychowdhury Suman Datta School of Electrical and Computer Engineering Georgia Institute of TechnologyAtlantaUSA

Low temperature complementary metal oxide semiconductor(CMOS)or cryogenic CMOS is a promising avenue for the continuation of Moore’s law while serving the needs of high performance *** temperature as a control“knob”to steepen the subthreshold slope behavior of CMOS devices,the supply voltage of operation can be reduced with no impact on operating *** the optimal threshold voltage engineering,the device ON current can be further enhanced,translating to higher *** this article,the experimentally calibrated data was adopted to tune the threshold voltage and investigated the power performance area of cryogenic CMOS at device,circuit and system *** also presented results from measurement and analysis of functional memory chips fabricated in 28 nm bulk CMOS and 22 nm fully depleted silicon on insulator(FDSOI)operating at cryogenic ***,the challenges and opportunities in the further development and deployment of such systems were discussed.

关键词： cryogenic CMOS Design technology co-optimization High performance computing Parameter variation Threshold voltage engineering cryogenic memories Interconnects

来源：

维普期刊数据库评论

在线全文

维普期刊数据库

学校读者我要写书评

暂无评论

欢迎您,

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

在线全文

在线全文

请选择保存的检索档案：

请选择收藏分类：

通借通还

欢迎您,

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

在线全文

在线全文

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：