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chip-level MMSE Equalization for CDMA Downlink

The Journal of China Universities of Posts and Telecommunications 2005年第2期12卷 82-86页

作者： ZHANG Yi GU Jian YANG Da-cheng Beijing University of Posts and Telecommunications Beijing 100876 P.R. China

This work is focused on the structure design of MMSE linear equalizers in the downlink of CDMA-based multi-user communication systems. Previous work was mostly focused on the performance comparison between ZF and MMSE linear equalizers and the conclusion is that the performance based on MMSE criterion is much better than that based on ZF one. In this paper, we only discuss MMSE equalizer and a new block structure of MMSE linear equalizer is derived from the traditional structure of this kind of equalizer. Furthermore, a block MMSE linear equalizer is improved through using the overlap-save technique. Simulation results shaw that the average performance of improved block MMSE linear equalizers is better than those of the block MMSE equalizers and traditional MMSE equalizers. At the same time, the computation complexity of all these MMSE equalizers is given. It is shown that the comple：rity of proposed block MMSE equalizers is lower than that of the traditional equalizers with optimal delay, D, when the length of the filter in traditional MMSE equalizers equals the block size of block MMSE equalizers.

关键词： MMSE ZF equalization chip-level overlap

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chip-level space-time equalization receiver scheme for MIMO HSDPA systems

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Journal of Southeast University(English Edition) 2004年第2期20卷 135-138页

作者：周志刚程时昕陈明东南大学移动通信国家重点实验室南京210096

A chip-level space-time equalization receiver scheme is proposed for multiple-input multiple-output high-speed downlink packet access (MIMO HSDPA) systems to jointly combat the co-channel interference and the inter-code interference. A fractional sample equalizer is also derived to further improve the performance of the receiver. Performance analysis and the calculation of the output signal to interference ratio (SINR) at each receiver antenna are presented to help direct the design of equalization weight in a more optimal manner. System simulations demonstrate the significant performance gain over conventional Rake receiver and high potential of MIMO HSDPA for high-data-rate packet transmission.

关键词： multiple-input multiple-output (MIMO) chip-level interference minimum mean square error (MMSE) weight space-time equalization

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IDMA Based on Deterministic Interleavers

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International Journal of Communications, Network and System Sciences 2010年第1期3卷 94-97页

作者： Shu-Ming TSENG 不详

Previously, the interleavers is generated randomly for users of Interleave Division Multiple Access (IDMA) systems. Therefore, transmitting the entire chip-level interleaver matrix or power interleaver generation is required, which either adds redundancy or increases delay. In this paper, we propose to use deterministic chip-level interleavers for multiple users of IDMA systems. These chip-level interleavers are modified from single-user symbol-level interleavers for turbo codes. The receiver can generate the chip-level interleavers for user k automatically without the redundancy of transmitting the entire interleaver matrix or the delay of generating power interleavers. Simulation results show that the proposed deterministic–interleaver-based IDMA performance is better than Gold-code-based CDMA in the multipath environment.

关键词： chip-level Interleaver Deterministic IDMA Turbo Code

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