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A Loop-Based Apparatus for At-Speed self-testing

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Journal of Computer Science & Technology 2001年第3期16卷 278-285页

作者：李晓维张英相等 InstituteofComputingTechnology TheChineseAcademyofSciencesBeijing100080P.R.China DepartmentofElectricalandElectronicEngineering UniversityofHongKongPokfulamRoadHongKongP.R.CHin

At-speed testing using external tester requires an expensive equipment, thus built-in self-test (BIST) is an alternative technique due to its ability to perform on-chip at-speed self-testing. The main issue in BIST for at-speed testing is to obtain high delay fault coverage with a low hardware overhead. This paper presents an improved loop-based BIST scheme, in which a configurable MISR (multiple-input signature register) is used to generate test-pair sequences. The structure and operation modes of the BIST scheme are described. The topological properties of the state-transit ion- graph of t he proposed B IS T scheme are analyzed. B ased on it, an approach to design and efficiently implement the proposed BIST scheme is developed. Experimental results on academic benchmark circuits are presented to demonstrate the effectiveness of the proposed BIST scheme as well as the design approach.

关键词： built-in self-test at-speed test multiple input shift register state transition graph

Design-for-testability Features and test Implementation of a Giga Hertz General Purpose Microprocessor

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Journal of Computer Science & Technology 2008年第6期23卷 1037-1046页

作者：王达胡瑜李华伟李晓维 Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences Graduate University of Chinese Academy of Sciences

This paper describes the design-for-testability （DFT） features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test （BIST） circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops （PLL） to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design, the test strategies for this case are quite complex, with complicated automatic test pattern generation （ATPG） and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing （HVM） DFT plan to meet high quality test goals as well as slow test power consumption and cost.

关键词： microprocessor design-for-testability test generation built-in self-test at-speed testing

Low Cost BIST Scheme Using LFSR-RC Reseeding

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Journal of Harbin Institute of Technology(New Series) 2015年第3期22卷 57-62页

作者： Bin Zhou Mingxue Huo Xinchun Wu Research Center of Basic Space Science Harbin Institute of Technology Dept. of Microelectronics Science and Technology Harbin Institute of Technology School of Information Science and Technology Southwest Jiaotong University

A novel BIST scheme for reducing the test storage( TS) is presented. The proposed approach relies on a two-dimensional compression scheme,which combines the advantages of the previous LFSR reseeding scheme and test set embedding technique based on ring counters( RCs) to improve the encoding efficiency. It presents a general method to determine the probability of encoding as a function of the number of specified bits in the test cube,the length of the LFSR and the width of the test set,and conclude that the probability of encoding a n-bit test cube with s specified bits using a( smax+ 1 + 20 / n)-stage LFSR with a fixed polynomial is1- 10-6. Experimental results for the ISCAS '89 benchmark circuits show that compared with the previous schemes,the proposed scheme based on LFSR-RC reseeding requires 57% less TS and 99. 1% test application time( TAT) with simple and uniform BIST control logic.

关键词： built-in self-test linear feedback shift register(LFSR) ring counters(RCs) test compression

The testing of multiple RAM Cores in Soc system

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The testing of multiple RAM Cores in Soc system

On the Input Probability for built-in test

2006 8th International Conference on Solid-State and Integrated Circuit Technology

作者： Wang Ying Wang Hong Shenyang Institute of Automation Chinese Academy of Sciences Graduate University of Chinese Academy of Sciences Information Engineering School Shenyang Institute of Chemical Technology

ISBN: (纸本)1424401607

＜正＞*** The development of the sub-micro technology makes it possible that the manufacturer of ASIC integrates IP into a single *** embedded memory is difficult to test because of the compact ***,BIST and processor-based are the mainly three *** BIST method decreases the test time by sacrificing the *** BIST has been the main test method due to the better *** cost of the area and pad is large if every memory possesses a BIST controller in the *** paper adopts a BIST controller to control dozens of *** method has the advantage of better flexibility,shorter time and lower area.

关键词： System testing built-in self-test Communication system control Read-write memory Manufacturing Application specific integrated circuits Random access memory Semiconductor device measurement Costs Control systems

来源： cnki会议评论

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The Journal of China Universities of Posts and Telecommunications 1994年第2期1卷 30-35页

作者： DingJin HuJiandong TrainingCenter BeijingofPostsandTelecommunicationsBeijing100088P.R.China TrainingCenter BeijingofPos

in this paper ,based on the butlt-in self-test technique to logic circuil ,a nme approach is pro-posed to optimize input probability of digital circuit. After the worst faults are found and their circuitmodel are created the output signals of these models will be compressed by “1” counter. Fault detectprobabilities for the worst faults can be obtained by analyzing compact data. Finally, using the relationbetween the input probability and the fault detect probabilily ,we propose a new algorithm to optimzethe primary input probainlily of the circuit. So the shortest test length can he received.

关键词： built-in self-test fault detect signal compaction probabilily optimum

A DFT Method for Single-Control testability of RTL Data Paths for BIST

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湖南大学学报（自然科学版） 2000年第S2期27卷 52-60页

作者： Toshimitsu Masuzawa Minoru lzutsu Hiroki Wada Hideo Fujiwara Graduate School of information Science Nara institute of Science and Technology 8916-5 Takayama IkomaNara630-0101Japan

This paper presents a new BIST method for RTL data paths based on single-control testability, a new concept of testability. The BIST method adopts hierarchical test. test pattern generators are placed only on primary inputs and test patterns are propagated to and fed into each module. test responses are similarly propagated to response analyzers placed only on primary outputs. For the propagation of test patterns and test responses paths existing in the data path are utilized. The DFT method for the single-control testability is also proposed. The advantages of the proposed method are high fault coverage (for single Stuck-at faults), low hardware overhead and capability of at-speed test. Moreover, test patterns generated by test pattern generators can be fed into each module at consecutive system clocks, and thus, the BIST can also detect some faults of other fault models (e.g., transition faults and delay faults) that require consecutive application of test patterns at speed of system clock.

关键词： built-in self-test design for testability RTL data path hierarchical test

testable Design and BIST Techniques for Systolic Motion Estimators in Transform Domain

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Journal of Electronic Science and Technology of China 2009年第4期7卷 291-296页

作者： Shyue-Kung Lu Wei-Yuan Liu Department of Electrical Engineering National Taiwan University of Science and Technology Taipei Taiwan China Department of Electronic Engineering Fu-Jen Catholic University Taipei Taiwan China

testable design techniques for systolic motion estimators based on M-testability conditions are proposed in this paper. The whole motion estimator can be viewed as a two-dimensional iterative logic array （ILA） of processing elements （PEs） and multiplying elements （MULs）. The functions of each PE and MUL are modified to be bijective to meet the M-testable conditions. The number of test patterns is 2^w, where w denotes the word length of a PE. The proposed testable design techniques are also suitable for built-in self-test implementation. According to experimental results, our approaches can achieve 99.27 % fault coverage. The area overhead is about 9 %. To verify our approaches, an experimental chip is also implemented.

关键词： built-in self-test design for testability fault coverage motion estimator.

A Novel BIST Approach for testing Input/Output Buffers in SoCs

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Journal of Electronic Science and Technology of China 2009年第4期7卷 322-325页

作者： Lei Chen Zhi-Ping Wen Zhi-Quan Zhang Min Wang Beijing Microelectronics Technology Institution Beijing 100076 China

A novel built-in self-test （BIST） approach to test the configurable input/output buffers in Xilinx Virtex series SoCs （system on a chip） using hard macro has been proposed in this paper. The proposed approach can completely detect single and multiple stuck-at gate-level faults as well as associated routing resources in I/O buffers. The proposed BIST architecture has been implemented and verified on Xilinx Virtex series FPGAs （field programmable gate configurations are required array）. Only total of 10 to completely test the I/O buffers of Virtex devices.

关键词： built-in self-test FPGA I/O buffers SoCs testing.