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An efficient adapting virtual intermediate instruction set towards optimized dynamic binary translator (DBT) system

Journal of Central South University 2012年第11期19卷 3118-3128页

作者：杨吟冬管海兵 Shanghai Key Laboratory of Scalable Computing and Systems(Shanghai Jiao Tong University)

A new efficient adapting virtual intermediate instruction set,V-IIS,is designed and implemented towards the optimized dynamic binary translator (DBT) *** the help of this powerful but previously little-studied component,DBTs can not only get rid of the dependence of machine(s),but also get better *** our systematical study and evaluation,experimental results demonstrate that if V-IIS is well designed,without affecting the other optimizing measures,this could make DBT's performance close to those who do not have intermediate *** study is an important step towards the grand goal of high performance "multi-source" and "multi-target" dynamic binary translation.

关键词： binary translation virtual intermediate instruction set dynamic binary translator (DBT)

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Dynamically Translating binary Code for Multi-Threaded Programs Using Shared Code Cache

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Journal of Electronic Science and Technology 2014年第4期12卷 434-438页

作者： Chia-Lun Liu Jiunn-Yeu Chen Wuu Yang Wei-Chung Hsu the Department of Computer Science National Chiao-Tung University

mc211vm is a process-level ARM-to-x86 binary translator developed in our lab in the past several years. Currently, it is able to emulate singlethreaded programs. We extend mc211vm to emulate multi-threaded programs. Our main task is to reconstruct its architecture for multi-threaded programs. Register mapping, code cache management, and address mapping in mc2llvm have all been modified. In addition, to further speed up the emulation, we collect hot paths, aggressively optimize and generate code for them at run time. Additional threads are used to alleviate the overhead. Thus, when the same hot path is walked through again, the corresponding optimized native code will be executed instead. In our experiments, our system is 8.8X faster than QEMU （quick emulator） on average when emulating the specified benchmarks with 8 guest threads.

关键词： ARM binary translation hot path,mc211vm multi-threaded program QEMU (quickemulator).

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维普期刊数据库

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Semantic Specification Of IA-64 Floating-point Instructions

Semantic Specification Of IA-64 Floating-point Instructions

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全国首届数字（虚拟）科技馆技术与应用学术研讨会

作者： Zhang Xuemeng Zhao Rongcai Pang Jianmin National Digital Switching System Engineering & Technological R&D Center ZhengZhou HeNan 450002 China

The IA-64 floating-point architecture provides performance enhancing features. However,the new features of IA-64 floating-point instructions make it difficult to map the semantics of machine instructions to higher-level intermediate representations,which is the key phase to binary *** paper presents an effective approach to semantic specification of IA-64 floating-point instructions,improving existing technologies according to characteristics of IA-64 floating-point *** particular,the authors take examples for a new algorithm and a few special floating-point instructions used in floating-point programming to describe the details of generating intermediate representation from IA-64 assembly ***,the relevant techniques are evaluated by five programs selected from the SPEC2000FP benchmarks with a static binary translator from IA-64 to *** can be seen from the preliminary results,the originality and technique soundness of the approach is proved.

关键词： semantic specification floating-point instructions IA-64 binary translation

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