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Machine Learning-Based Pruning Technique for Low Power approximate computing

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Computer Systems Science & Engineering 2022年第7期42卷 397-406页

作者： B.Sakthivel K.Jayaram N.Manikanda Devarajan S.Mahaboob Basha S.Rajapriya Department of Electronics and Communication Engineering Madurai Institute of Engg and TechnologySivagangaiTamilnadu630611India Pilecubes India Pvt Ltd. ChennaiTamilnaduIndia Department of Electronics and Communication Engineering Malla Reddy Engineering College(Autonomous)Secunderabad500100India Department of Electronics and Communication Engineering R.M.K.Engineering CollegeKavaraipettaiChennaiTamil Nadu601206India Department of Electronics and Communication Engineering K Ramakrishnan College of EngineeringKariyamanickam RdTamil Nadu621112India

approximate computing is a low power achieving technique that offers an additional degree of freedom to design digital *** is one of the types of approximate circuit design technique which removes logic gates or wires in the circuit to reduce power consumption with minimal insertion of *** this work,a novel machine learning(ML)-based pruning technique is introduced to design digital *** machine-learning algorithm of the random forest deci-sion tree is used to prune nodes selectively based on their input *** addi-tion,an error compensation value is added to the original output to reduce an error *** results proved the efﬁciency of the proposed technique in terms of area,power and error *** to conventional pruning,proposed ML pruning achieves 32%and 26%of the area and delay reductions in 8*8 multi-plier *** power image processing algorithms are essential in various applications like image compression and enhancement *** real-time evaluation,proposed ML optimized pruning is applied in discrete cosine transform(DCT).It is a basic element of image and video processing *** results on benchmark images show that proposed pruning achieves a very good peak signal-to-noise ratio(PSNR)value with a considerable amount of energy savings compared to other methods.

关键词： Machine learning pruning approximate computing PSNR

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Journal of Computer Science & Technology 2024年第1期39卷 63-81页

作者：陈章玉华宇左鹏飞孙园园郭云程 Wuhan National Laboratory for Optoelectronics School of Computer Science and TechnologyHuazhong University of Science and TechnologyWuhan 430074China

Image bitmaps,i.e.,data containing pixels and visual perception,have been widely used in emerging applica-tions for pixel operations while consuming lots of memory space and *** with legacy DRAM(dynamic ran-dom access memory),non-volatile memories(NVMs)are suitable for bitmap storage due to the salient features of high density and intrinsic ***,writing NVMs suffers from higher energy consumption and latency compared with read *** precise or approximate compression schemes in NVM controllers show limited performance for bitmaps due to the irregular data patterns and variance in *** observe the pixel-level similarity when writing bitmaps due to the analogous contents in adjacent *** exploiting the pixel-level similarity,we propose SimCom,an approximate similarity-aware compression scheme in the NVM module controller,to efficiently compress data for each write access *** idea behind SimCom is to compress continuous similar words into the pairs of base words with *** storage costs for small runs are further mitigated by reusing the least significant bits of base *** adaptively selects an appropriate compression mode for various bitmap formats,thus achieving an efficient trade-off be-tween quality and memory *** implement SimCom on GEM5/zsim with NVMain and evaluate the perfor-mance with real-world image/video *** results demonstrate the efficacy and efficiency of our SimCom with an efficient quality-performance trade-off.

关键词： approximate computing data compression memory architecture non-volatile memory

LMM:A Fixed-Point Linear Mapping Based approximate Multiplier for IoT

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Journal of Computer Science & Technology 2023年第2期38卷 298-308页

作者：吴莹温晨怡尹勋钊卓成 College of Information Science and Electronic Engineering Zhejiang UniversityHangzhou 310027China Key Laboratory of Collaborative Sensing and Autonomous Unmanned Systems of Zhejiang Province Hangzhou 310027 China

The development of IoT(Internet of Things)calls for circuit designs with energy and area efficiency for edge *** computing which trades unnecessary computation precision for hardware cost savings is a promising direction for error-tolerant ***,as frequently invoked basic modules which consume non-trivial hardware costs,have been introduced approximation to achieve distinct energy and area savings for data-intensive *** this paper,we propose a fixed-point approximate multiplier that employs a linear mapping technique,which enables the configurability of approximation levels and the unbiasedness of computation *** then introduce a dynamic truncation method into the proposed multiplier design to cover a wider and more fine-grained configuration range of approximation for more flexible hardware cost *** addition,a novel normalization module is proposed for the required shifting operations,which balances the occupied area and the critical path delay compared with normal *** introduced errors of our proposed design are analyzed and expressed by formulas which are validated by experimental *** evaluations show that compared with accurate multipliers,our proposed approximate multiplier design provides maximum area and power savings up to 49.70%and 66.39%respectively with acceptable computation errors.

关键词： approximate computing fixed-point linear mapping multiplier Internet of Things(IoT)

approximate Processing Element Design and Analysis for the Implementation of CNN Accelerators

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Journal of Computer Science & Technology 2023年第2期38卷 309-327页

作者：李彤姜红兰莫海韩杰刘雷波毛志刚 Department of Micro-Nano Electronics Shanghai Jiao Tong UniversityShanghai 200240China School of Integrated Circuits Tsinghua UniversityBeijing 100084China Department of Electrical and Computer Engineering University of AlbertaEdmontonAB T6G 1H9Canada

As a primary computation unit,a processing element(PE)is key to the energy efficiency of a convolutional neural network(CNN)*** advantage of the inherent error tolerance of CNNs,approximate computing with high hardware efficiency has been considered for implementing the computation units of CNN ***,individual approximate designs such as multipliers and adders can only achieve limited accuracy and hardware *** this paper,an approximate PE is dedicatedly devised for CNN accelerators by synergistically considering the data representation,multiplication and *** approximate data format is defined for the weights using stochastic *** data format enables a simple implementation of multiplication by using small lookup tables,an adder and a *** approximate accumulators are further proposed for the product accumulation in the *** with the exact 8-bit fixed-point design,the proposed PE saves more than 29%and 20%in power-delay product for 3×3 and 5×5 sum of products,***,compared with the PEs consisting of state-of-the-art approximate multipliers,the proposed design shows significantly smaller error bias with lower hardware ***,the application of the approximate PEs in CNN accelerators is analyzed by implementing a multi-task CNN for face detection and *** conclude that 1)an approximate PE is more effective for face detection than for alignment,2)an approximate PE with high statistically-measured accuracy does not necessarily result in good quality in face detection,and 3)properly increasing the number of PEs in a CNN accelerator can improve its power and energy efficiency.

关键词： approximate computing convolutional neural network(CNN) sum of products(SoP) data representation multiplier

Efficient and optimized approximate GDI full adders based on dynamic threshold CNTFETs for specific least significant bits

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Frontiers of Information Technology & Electronic Engineering 2023年第4期24卷 599-616页

作者： Ayoub SADEGHI Razieh GHASEMI Hossein GHASEMIAN Nabiollah SHIRI Department of Electrical Engineering Shiraz BranchIslamic Azad UniversityShiraz ***Iran School of Electrical Engineering Iran University of Science and TechnologyTehran ***Iran Department ofElectrical and Electronic Engineering Shiraz University of TechnologyShiraz ***Iran

Carbon nanotube field-effect transistors(CNTFETs) are reliable alternatives for conventional transistors, especially for use in approximate computing(AC) based error-resilient digital circuits. In this paper, CNTFET technology and the gate diffusion input(GDI) technique are merged, and three new AC-based full adders(FAs) are presented with 6, 6, and 8 transistors, separately. The nondominated sorting based genetic algorithm II(NSGA-II) is used to attain the optimal performance of the proposed cells by considering the number of tubes and chirality vectors as its variables. The results confirm the circuits' improvement by about 50% in terms of power-delay-product(PDP) at the cost of area occupation. The Monte Carlo method(MCM) and 32-nm CNTFET technology are used to evaluate the lithographic variations and the stability of the proposed circuits during the fabrication process, in which the higher stability of the proposed circuits compared to those in the literature is observed. The dynamic threshold(DT) technique in the transistors of the proposed circuits amends the possible voltage drop at the outputs. Circuitry performance and error metrics of the proposed circuits nominate them for the least significant bit(LSB) parts of more complex arithmetic circuits such as multipliers.

关键词： Carbon nanotube field-effect transistor(CNTFET) Optimization algorithm Nondominated sorting based genetic algorithm II(NSGA-II) Gate diffusion input(GDI) approximate computing

Design of Precise Multiplier Using Inexact Compressor for Digital Signal Processing

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Computer Systems Science & Engineering 2022年第8期42卷 619-638页

作者： Nagarajan Shanmugam Vijeyakumar Krishnasamy Natarajan Kalaiselvi Sundaram Saravanakumar Natarajan Electronics and Communication Engineering Dr.Mahalingam College of Engineering and TechnologyPollachi642003Tamil NaduIndia

In the recent years,error recovery circuits in optimized data path units are adopted with approximate computing *** this paper the novel multipliers have effective utilization in the newly proposed two different 4:2 approximate compressors that generate Error free Sum(ES)and Error free Carry(EC).Proposed ES and Proposed EC in 4:2 compressors are used for performing Partial Product(PP)*** structural arrangement utilizes Dadda structure based *** to the regularity of PP arrangement Dadda multiplier is chosen for compressor implementation that favors easy standard cell ASIC *** this,the proposed compression idealogy are more effective in the smallest n columns,and the accurate compressor in the remaining most significant *** limits the error in the multiplier output to be not more than 2n for an n X n *** choice among the proposed compressors is decided based on the significance of the sum and carry signals on the multiplier *** an enhancement to the proposed multiplier,we introduce two Area Efficient(AE)variants viz.,Proposed-AE(P-AE),and P-AE with Error Recovery(P-AEER).The proposed basic P-AE,and P-AEER designs exhibit 46.7%,52.9%,and 52.7%PDP reduction respectively when compared to an approximate multiplier of minimal error type and are designed with 90nm ASIC *** proposed design and their performance validation are done by using Cadence *** performance evaluations are carried out using cadence encounter with 90nm ASIC *** proposed-basic P-AEA and P-AEER designs demonstrate 46.7%,52.9%and 52.7%PDP reduction compared to the minimal error approximate *** proposed multiplier is implemented in digital image processing which revealed 0.9810 Structural SIMilarity Index(SSIM),to the least,and less than 3%deviation in ECG signal processing application.

关键词： approximate computing precise multiplier PP compression area-efficient error-recovery approach

A Dynamic Multi-Attribute Resource Bidding Mechanism with Privacy Protection in Edge computing

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计算机、材料和连续体（英文） 2023年第4期75卷 373-391页

作者： Shujuan Tian Wenjian Ding Gang Liu Yuxia Sun Saiqin Long Jiang Zhu Xiangtan University Xiangtan411105China Key Laboratory of Hunan Province for Internet of Things and Information Security Xiangtan411105China Hunan International Scientific and Technological Cooperation Base of Intelligent Network Xiangtan411105China Hunan University Changsha410082China Jinan University Guangzhou510632China

In edge computing,a reasonable edge resource bidding mechanism can enable edge providers and users to obtain benefits in a relatively fair *** maximize such benefits,this paper proposes a dynamic multiattribute resource bidding mechanism(DMRBM).Most of the previous work mainly relies on a third-party agent to exchange information to gain optimal *** isworth noting thatwhen edge providers and users trade with thirdparty agents which are not entirely reliable and trustworthy,their sensitive information is prone to be ***,the privacy protection of edge providers and users must be considered in the dynamic pricing/transaction process,which is also very ***,this paper first adopts a privacy protection algorithm to prevent sensitive information from *** the premise that the sensitive data of both edge providers and users are protected,the prices of providers fluctuate within a certain ***,users can choose appropriate edge providers by the price-performance ratio(PPR)standard and the reward of lower price(LPR)standard according to their *** two standards can be evolved by two evaluation ***,this paper employs an approximate computing method to get an approximate solution of DMRBM in polynomial ***,this paper models the bidding process as a non-cooperative game and obtains the approximate optimal solution based on two standards according to the game *** the extensive experiments,this paper demonstrates that the DMRBM satisfies the individual rationality,budget balance,and privacy protection and it can also increase the task offloading rate and the system benefits.

关键词： Edge computing approximate computing nash equilibrium privacy protection

Efficient Energy Optimized Faithful Adder with Parallel Carry Generation

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Computers, Materials & Continua 2022年第2期70卷 2543-2561页

作者： K.N.Vijeyakumar S.Maragatharaj Dr.Mahalingam College of Engineering and Technology PollachiTamilnaduIndia Dhirajlal Gandhi College of Technology SalemTamilnaduIndia

Abstract:approximate computing has received significant attention in the design of portable CMOS hardware for error-tolerant *** work proposes an approximate adder that to optimize area delay and achieve energy efficiency using Parallel Carry(PC)generation ***‘n’bits in input,the proposed algorithm use approximate addition for least n/2 significant bits and exact addition for most n/2 significant bits.A simple OR logic with no carry propagation is used to implement the approximate *** the exact part,addition is performed using 4-bit adder blocks that implement PC at block level to reduce node capacitance in the critical *** reveal that the maximum error of the proposed adder confines not more than 2n/*** an enhancement of the proposed algorithm,we use the Error Recovery(ER)module to reduce the average *** results of Proposed-PC(P-PC)and Proposed-PCER(P-PCER)adders with n-16 in 180nm Application Specific Integrated Circuit(ASIC)PDK technology revealed 44.2%&41.7%PDP reductions and 43.4%&40.7%ADP reductions,respectively compared to the latest best approximate design *** functional and driving effectiveness of proposed adders are examined through digital image processing applications.

关键词： Application-specific integrated circuit approximate computing power dissipation energy dissipation image processing

Survey of Distributed computing Frameworks for Supporting Big Data Analysis

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Big Data Mining and Analytics 2023年第2期6卷 154-169页

作者： Xudong Sun Yulin He Dingming Wu Joshua Zhexue Huang College of Computer Science and Software Engineering Shenzhen UniversityShenzhen 518060China Guangdong Laboratory of Artificial Intelligence and Digital Economy(SZ) Shenzhen 518107China

Distributed computing frameworks are the fundamental component of distributed computing *** provide an essential way to support the efficient processing of big data on clusters or *** size of big data increases at a pace that is faster than the increase in the big data processing capacity of ***,distributed computing frameworks based on the MapReduce computing model are not adequate to support big data analysis tasks which often require running complex analytical algorithms on extremely big data sets in *** performing such tasks,these frameworks face three challenges:computational inefficiency due to high I/O and communication costs,non-scalability to big data due to memory limit,and limited analytical algorithms because many serial algorithms cannot be implemented in the MapReduce programming *** distributed computing frameworks need to be developed to conquer these *** this paper,we review MapReduce-type distributed computing frameworks that are currently used in handling big data and discuss their problems when conducting big data *** addition,we present a non-MapReduce distributed computing framework that has the potential to overcome big data analysis challenges.

关键词： distributed computing frameworks big data analysis approximate computing MapReduce computing model