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A Low-Power 12-Bit SAR ADC for analog convolutional kernel of Mixed-Signal CNN Accelerator

Computers, Materials & Continua 2023年第5期75卷 4357-4375页

作者： Jungyeon Lee Malik Summair Asghar HyungWon Kim Department of Electronics College of Electrical and Computer EngineeringChungbuk National UniversityCheongju28644Korea Department of Electrical and Computer Engineering COMSATS University IslamabadAbbottabad CampusUniversity RoadTobe CampAbbottabad22044Pakistan

As deep learning techniques such as convolutional Neural Networks(CNNs)are widely adopted,the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip(SoC).Although conventional CNN accelerators can reduce the computational time of learning and inference tasks,they tend to occupy large chip areas due to many multiply-and-accumulate(MAC)operators when implemented in complex digital circuits,incurring excessive power *** overcome these drawbacks,this work implements an analog convolutional filter consisting of an analog multiply-and-accumulate arithmetic circuit along with an analog-to-digital converter(ADC).This paper introduces the architecture of an analog convolutional kernel comprised of low-power ultra-small circuits for neural network accelerator *** is an essential component of the analog convolutional kernel used to convert the analog convolutional result to digital values to be stored in *** work presents the implementation of a highly low-power and area-efficient 12-bit Successive Approximation Register(SAR)*** most other SAR-ADCs with differential structure;the proposed ADC employs a single-ended capacitor array to support the preceding single-ended max-pooling circuit along with minimal power *** SARADCimplementation also introduces a unique circuit that reduces kick-back noise to increase *** was implemented in a test chip using a 55 nm CMOS *** demonstrates that the proposed ADC reduces Kick-back noise by 40%and consequently improves the ADC’s resolution by about 10%while providing a near rail-to-rail dynamic rangewith significantly lower power consumption than conventional *** ADC test chip shows a chip size of 4600μm^(2)with a power consumption of 6.6μW while providing an signal-to-noise-and-distortion ratio(SNDR)of 68.45 dB,corresponding to an effective number of bits(ENOB)of 11.07 bits.

关键词： Convolution neural networks split-capacitor-based digital-toanalog converter(DAC) SAR analog-to-digital converter artificial intelligence system-on-chip analog convolutional kernel

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