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vlsi implementation of a Single-Chip DVB-C Demodulator

Journal of Semiconductors 2005年第7期26卷 1309-1316页

作者：田骏骅沈泊苏佳宁李铮李建郭亚炜章倩苓复旦大学专用集成电路与系统国家重点实验室上海200433 上海微科集成电路有限公司上海200433

A single-chip DVB-C quadrature amplitude modulation（QAM） demodulator is proposed,which integrates a 3.3V 10bit 40MSPS analog-to-digital converter and a forward error correction decoder. The demodulator chip can support 4-256 QAM with variable bit rate up to 80Mbps. It features a wide carrier offset acquisition range,optimal demodulation algorithm,and small circuit area. The chip is implemented in SMIC 0.25μm 1P5M mixed-signal CMOS technology with a die size of 3.5mm×3. 5mm. The maximum power consumption is 447mW.

关键词： QAM demodulator vlsi implementation carrier recovery blind equalization

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维普期刊数据库

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A Fast Algorithm of the DCT and IDCT for vlsi implementation

A Fast Algorithm of the DCT and IDCT for VLSI Implementation

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1996 3rd International Conference on Signal Processing(ICSP’96)

作者： Hong Ying Hou Zhaohuan Institute of Acoustics Chinese Academy of Sciences

ISBN: (纸本)0780329120

＜正＞Since DCT performs very close to the statistically optimal Karhunen-Loeve Transform（KLT）,it is widely used in digital signal processing,especially for speech and image data *** DCT algorithms and vlsi architectures for real-time computation capabilities are required *** is known that vlsi implementation of distributed arithmetic is very efficient for computing ***,an algorithm is presented to convert the DCT and inverse DCT（IDCT） to *** implementation of the algorithm has same advantage as any implementation using distributed arithmetic.

关键词： vlsi discrete cosine transforms inverse problems transform coding digital signal processing chips data compression speech coding image coding digital arithmetic convolution number theory IDCT DCT vlsi implementation fast algorithm digital signal processing statistically optimal Karhunen-Loeve transform image data compression speech compression vlsi architectures real-time computation distributed arithmetic inverse DCT skew-convolution number theoretic transforms

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Power Prediction of vlsi Circuits Using Machine Learning

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Computers, Materials & Continua 2023年第1期74卷 2161-2177页

作者： E.Poovannan S.Karthik Department of ECE College of Engineering and TechnologySRM Institute of Science and TechnologyVadapalani CampusChennai600026TNIndia

The difference between circuit design stage and time requirements has broadened with the increasing complexity of the circuit.A big database is needed to undertake important analytical work like statistical method,heat research,and IR-drop research that results in extended running *** unit focuses on the assessment of test *** of the enormous number of successful designs for currentmodels and the unnecessary time required for every test,maximum energy ratings with all tests cannot be ***,test safety is important for producing trustworthy findings to avoid loss of output and harm to the ***,effective power assessment is only possible in a limited sample of pre-selected ***,a key objective is to find the experiments that might give the worst situations again for testing *** offers a machine-based circuit power estimation(MLCPE)system for the selection of *** distinct techniques of predicting are ***,to find testings with power dissipation,it forecasts the behavior of ***,the changemovement and energy data are linked to the semiconductor design,identifying small problem *** types of algorithms are *** particular,the methods *** findings show great accuracy and efficiency in *** enables such methods suitable for selecting the worst scenario.

关键词： Power estimation Machine learning circuit simulation vlsi implementation

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Analysis on parallel implementations of fixed-complexity sphere decoder

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Science China(Information Sciences) 2013年第4期56卷 155-165页

作者： WU Bin MASERA Guido vlsi Lab Dipartimento di ElettronicaPolitecnico di TorinoTorino 10129Italy

Sphere decoders are widely investigated for the implementation of multiple-input multiple-output(MIMO) *** a large number of sphere decoding algorithms,the fixed-complexity sphere decoder(FSD) exhibits remarkable advantages in terms of constant throughput and high flexibility of parallel *** this paper,we present a four-nodes-per-cycle parallel FSD architecture with balanced performance and hardware complexity,and several examples of vlsi implementation for different types of modulation and both real and complex signal *** aspects and architecture details are analyzed in order to present a hardware-level perspective of the FSD *** a variety of performance-complexity trade-offs are *** implementation results show that the proposed parallel FSD architecture is highly efficient and flexible,especially in the complex signal model.

关键词： MIMO detection fixed-complexity sphere decoder parallel architecture vlsi implementation

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A Novel Divider Based on Dual-Bit Algorithm

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Journal of Semiconductors 2004年第6期25卷 645-650页

作者：李侠孙慧章倩苓复旦大学专用集成电路与系统国家重点实验室上海200433

A novel divider based on dual-bit algorithm and its vlsi implementation are *** with the divider of MIPS microprocessor,it decreases the average executing cycles by 52.5% while its maximum delay is almost the same and its transistor count increases by 60%.Furthermore,the simulation result indicates that the power consumption decreases to 11.3% with the same processing ability.

关键词： dual-bit algorithm division vlsi implementation power consumption

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维普期刊数据库

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A High-Speed Area-Efficient Architecture for the Arithmetic in GF（2m）

A High-Speed Area-Efficient Architecture for the Arithmetic ...

引用

2006 8th International Conference on Solid-State and Integrated Circuit Technology

作者： Jian Wang Anping Jiang Department of Microelectronics Peking University

＜正＞Finite fields have been used for numerous applications including error-control coding and *** paper presents a high-speed area-efficient architecture for arithmetic that can support arbitrary irreducible polynomials in GF（2m）. The arithmetic unit can perform the Galois field arithmetic operations of addition,subtraction, multiplication,squaring,inversion and *** least significant bit first（LSB-first） scheme for modular multiplication and the extended Euclid’s algorithm for modular inversion are both modified for the arithmetic *** architecture has been implemented using 0.18-μm CMOS standard cell library,the clock frequency can reach 300MHz for a 512-bit arithmetic *** gate count of the circuit is only 48528.

关键词： Cryptography Galois fields Euclid’s algorithm vlsi implementation

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