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Area-Optimized BCD-4221 VSLI Adder Architecture for High-Performance Computing

Journal of Harbin Institute of Technology(New Series) 2024年第3期31卷 31-38页

作者： Dharamvir Kumar Manoranjan Pradhan Department of Electronics&Telecommunication Engineering Veer Surendra Sai University of TechnologyBurla 768018India

Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic *** can be used in banking,commercial and financial transactions,scientific measurements,*** article presents the Very Large Scale Integration(vlsi)design of Binary Coded Decimal(BCD)-4221 area-optimized adder architecture using unconventional BCD-4221 *** BCD number representations such as BCD4221 also possess the additional advantage of more effectively representing the 10's complement representation which can be used to accelerate the decimal arithmetic *** design uses a binary Carry Lookahead Adder(CLA)along with some other logic blocks which are required to perform internal calculations with BCD-4221 *** design is verified by using Xilinx Vivado *** results have been obtained by Cadence Genus16.1 synthesis tool using 90 nm *** performance parameters such as area,power,delay,and area-delay Product(ADP)are compared with earlier reported *** proposed circuit shows significant area and ADP improvement over existing designs.

关键词： vlsi design unconventional BCD representation BCD adder circuit computer arithmetic digital circuit

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Low power DCVSL circuits employing AC power supply

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Science in China(Series F) 2002年第3期45卷 232-240页

作者：吴训威杭国强 Massoud Pedram Institute of Circuits and Systems Ningbo University Ningbo 315211 China

In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design, which adopts a gradually changing power clock. First, we discuss the algebraic expressions and the corresponding properties of clocked power signals. Then the design procedure is summed up for converting complementary CMOS logic gates employing DC power to the power-clocked CMOS gates employing AC power. On this basis, the design of differential cas-code voltage switch logic (DCVSL) circuits employing AC power clocks is proposed. The PSPICE simulations using a sinusoidal power-clock demonstrate that the designed power-clocked DCVSL circuit has a correct logic function and low power characteristics. Finally, an interface circuit to convert clocked signals into the standard logic levels of a CMOS circuit is proposed, and its validity is verified by computer simulations.

关键词： vlsi design low power technique AC power clocked DCVSL circuit.

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维普期刊数据库

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Preface

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Journal of Computer Science & Technology 2005年第2期20卷 145-146页

作者： Xiao-WeiLi Professor InstituteofComputingTechnologyChineseAcademyofSciencesAsiaandPacificRegionalTTTCVice-ChairIEEEComputerSociety

design, test and verification of today's vlsi circuits continuously challenge engineers in every IC design cycle. Based on the Twelfth IEEE Asian Test Symposium (Xi'an, November 16-19, 2003) and the Fourth IEEE Workshop on RTL and High-Level Testing (Xi'an, November 20-21, 2003), we are encouraged to organized a special issue on these topices.

关键词： vlsi design vlsi circuits

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