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Random testing for system-level functional verification of system-on-chip

Journal of Systems Engineering and Electronics 2009年第6期20卷 1378-1383页

作者： Ma Qinsheng Cao Yang Yang Jun Wang Min School of Electronic Information Wuhan Univ. Wuhan 430079 P. R. China State Key Lab. of Software Engineering Wuhan Univ. Wuhan 430072 P. R. China Second Dept. Commanding Communications Academy Wuhan 430010 P. R. China

In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is *** validity of this method is proven ***, testcases are generated according to many approaches of ***, the testbench for the system-level verification according to the proposed method is designed by using advanced modeling ***, under the circumstances that the testbench generates testcases quickly, the hardware/software co-simulation and co-verification can be implemented and the hardware/software partitioning planning can be evaluated *** comparison method is put to use in the evaluation approach of the testing *** evaluation result indicates that the efficiency of the partition testing is better than that of the random testing only when one or more subdomains are covered over with the area of errors, although the efficiency of the random testing is generally better than that of the partition *** experimental result indicates that this method has a good performance in the functional coverage and the cost of testing and can discover the functional errors as soon as possible.

关键词： vlsi circuit verification random process function testing system-on-chip system-level.

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Recursive bisection placement algorithm with the predicted wirelength

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Journal of Southeast University(English Edition) 2008年第4期24卷 462-467页

作者：蒿杰马鸿彭思龙中国科学院自动化研究所国家专用集成电路设计工程研究中心北京100190

To obtain a better placement result, a partitioning-based placement algorithm with wirelength prediction called HJ-Pl is presented. A new method is proposed to estimate proximity of interconnects in a netlist, which is capable of predicting not only short interconnects but long interconnects accurately. The predicted wirelength is embedded into the partitioning tool of bisection-based global placement, which can guide our placement towards a solution with shorter interconnects. In addition, the timing objective can be handled within the algorithm by minimizing the critical path delay. Experimental results show that, compared to Capol0. 5, mPL6, and NTUplace, HJ-P1 outperforms these placers in terms of wirelength and run time. The improvements in terms of average wirelength over Capo10. 5, mPL6 and NPUplace are 13%, 3%, and 9% with only 19%, 91%, and 99% of their runtime, respectively. By integrating the predicted wirelength-driven clustering into Capo10. 5, the placer is able to reduce average wirelength by 3%. The timing-driven HJ-P1 can reduce the critical path delay by 23%.

关键词： hierarchy interconnect placement vlsi circuit wirelength prediction

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