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Implementation of vlsi on Signal Processing-Based Digital Architecture Using AES Algorithm

Computers, Materials & Continua 2023年第3期74卷 4729-4745页

作者： Mohanapriya Marimuthu Santhosh Rajendran Reshma Radhakrishnan Kalpana Rengarajan Shahzada Khurram Shafiq Ahmad Abdelaty Edrees Sayed Muhammad Shafiq Department of CSE Coimbatore Institute of TechnologyCoimbatore641014India Department of CSE Karpagam Academy of Higher EducationCoimbatore641021India Department of Electronics and Communication Engineering Veltech Multitech Dr.Rangarajan Dr.Sakunthala EngineeringChennai600062India Faculty of Computing The Islamia University of BahawalpurBahawalpur63100Pakistan Industrial Engineering Department College of EngineeringKing Saud UniversityP.O.Box 800Riyadh11421Saudi Arabia Department of Information and Communication Engineering Yeungnam UniversityGyeongsan38541Korea

Continuous improvements in very-large-scale integration(vlsi)technology and design software have significantly broadened the scope of digital signal processing(DSP)applications.The use of application-specific integrated circuits(ASICs)and programmable digital signal processors for many DSP applications have changed,even though new system implementations based on reconfigurable computing are becoming more complex.Adaptable platforms that combine hardware and software programmability efficiency are rapidly maturing with discrete wavelet transformation(DWT)and sophisticated computerized design techniques,which are much needed in today’s modern world.New research and commercial efforts to sustain power optimization,cost savings,and improved runtime effectiveness have been initiated as initial reconfigurable technologies have emerged.Hence,in this paper,it is proposed that theDWTmethod can be implemented on a fieldprogrammable gate array in a digital architecture(FPGA-DA).We examined the effects of quantization on DWTperformance in classification problems to demonstrate its reliability concerning fixed-point math implementations.The Advanced Encryption Standard(AES)algorithm for DWT learning used in this architecture is less responsive to resampling errors than the previously proposed solution in the literature using the artificial neural networks(ANN)method.By reducing hardware area by 57%,the proposed system has a higher throughput rate of 88.72%,reliability analysis of 95.5%compared to the other standard methods.

关键词： vlsi A ES discrete wavelet transformation signal processing

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Performance Measurement of Energy Efficient and Highly Scalable Hybrid Adder

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Computer Systems Science & Engineering 2023年第6期45卷 2659-2672页

作者： B.Annapoorani P.Marikkannu Anna University Regional Campus CoimbatoreTamilnaduIndia

The adders are the vital arithmetic operation for any arithmetic operations like multiplication,subtraction,and division.Binary number additions are performed by the digital circuit known as the adder.In vlsi(Very Large Scale Integration),the full adder is a basic component as it plays a major role in designing the integrated circuits applications.To minimize the power,various adder designs are implemented and each implemented designs undergo defined drawbacks.The designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is more.To overcome such issues and to obtain better performance,a novel parallel adder is proposed.The design of adder is initiated with 1 bit and has been extended up to 32 bits so as verify its scalability.This proposed novel parallel adder is attained from the carry look-ahead adder.The merits of this suggested adder are better speed,power consumption and delay,and the capability in driving.Thus designed adders are verified for different supply,delay,power,leakage and its performance is found to be superior to competitive Manchester Carry Chain Adder(MCCA),Carry Look Ahead Adder(CLAA),Carry Select Adder(CSLA),Carry Select Adder(CSA)and other adders.

关键词： vlsi full adder carry look ahead adder novel parallel adder

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vlsi architecture of a K-best detector for MIMO-OFDM wireless communication systems

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Journal of Semiconductors 2009年第7期30卷 96-99页

作者：鉴海防石寅 Institute of Semiconductors Chinese Academy of Sciences Graduate University of the Chinese Academy of Sciences

The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity.In this paper, a new K-best vlsi architecture is presented.In the proposed architecture, the metric computation units（MCUs） expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches＇ ascending order by their local distances.Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines.Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly.Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors.Hence, it is an efficient solution to the K-best detector＇s vlsi implementation for high-throughput MIMO-OFDM systems.

关键词： MIMO-OFDM VBLAST K-best detector vlsi

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vlsi Implementation of Area and Power Efficient Digital Control Circuit for HF RFID Tag Chip

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Chinese Journal of Electronics 2020年第1期29卷 82-88页

作者： WANG Deming HU Jianguo WANG Jianhui DING Yanyu WU Jing School of Physics and Telecommunication Engineering South China Normal University Hong Kong Applied Science and Technology Research Institute Company Limited

A fully integrated area efficient digital control circuit based on the ISO/IEC 15693 protocol is proposed for high frequency RFID tag chip. The proposed circuit is mainly composed of pulse position modulation decoder, Manchester encoder, anticonllision, low power circuit and other control logic. It supports six different data rates, namely, low or high data rate with one subcarrier(6.62 or 26.48 Kbit/s), low or high data rate with two subcarriers(6.67 or 26.69 Kbit/s), fast data rate with one subcarrier(13.24 or 52.97 Kbit/s). The proposed digital control circuit was integrated in an RFID tag IC and was fabricated using a 0.18-μm 2 P6 M CMOS process with an area of 306μm by 326μm which is smaller than the existing designs. Besides of small area, the circuit has an advantage of low power with a power consumption of less than 50μW.

关键词： RFID Digital control circuit Low power vlsi

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vlsi Design for High-Precision Three-Dimensional Depth Perception Chip

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Chinese Journal of Electronics 2021年第3期30卷 556-560页

作者： GE Chenyang YAO Huimin ZHOU Yanhui DENG Pengchao Institute of Artificial Intelligence and Robotics Xi'an Jiaotong University Institute of electromagnetic and information technology Xi'an Jiaotong University

This paper presents a Very large scale integration(vlsi) design method for Three-dimensional(3 D) depth perception chip based on infrared coding structure light. The primary sub-modules on the chip contain the speckle pattern preprocessing module, blockmatching disparity estimation, depth mapping and postprocessing. The chip employs pipelining technology,and after Application specific integrated circuit(ASIC)verification, it proves that our chip has more advantages in performance of depth precision(12 bits, 1 mm @ 1 m),image resolution(1280×960), time delay(less than 17 ms),range limit(0.4～6 m). It also can generate more stable and smooth depth map in real-time, which can be used in 3 D recognition, motion capture or scene perception.

关键词： Semiconductor integrated circuits Image recognition Computer vision and image processing techniques 3D depth perception structure light coding vlsi ASIC

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A Novel vlsi Architecture for Real-Time Line-Based Wavelet Transform Using Lifting Scheme

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Journal of Computer Science & Technology 2007年第5期22卷 661-672页

作者：刘凯王柯俨李云松吴成柯 School of Computer Science Xidian University Xi'an 710071China National Key Laboratory of Integrated Service Networks Xidian University Xi'an 710071China

In this paper, we propose a vlsi architecture that performs the line-based discrete wavelet transform （DWT） using a lifting scheme. The architecture consists of row processors, column processors, an intermediate buffer and a control module. Row processor and Column processor work as the horizontal and vertical filters respectively. Intermediate buffer is composed of five FIFOs to store temporary results of horizontal filter. Control module schedules the output order to external memory. Compared with existing ones, the presented architecture parallelizes all levels of wavelet transform to compute multilevel DWT within one image transmission time, and uses no external but one intermediate buffer to store several line results of horizontal filtering, which decreases resource required significantly and reduces memory efficiently. This architecture is suitable for various real-time image/video applications.

关键词： line-based wavelet transforms lifting-based vlsi

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A hybrid multi-objective PSO algorithm with local search strategy for vlsi partitioning

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Frontiers of Computer Science 2014年第2期8卷 203-216页

作者： Wenzhong GUO Genggeng LIU Guolong CHEN Shaojun PENG College of Mathematics and Computer Science Fuzhou University Fuzhou 350116 China

Very large scale integration （vlsi） circuit par- titioning is an important problem in design automation of vlsi chips and multichip systems; it is an NP-hard combi- national optimization problem. In this paper, an effective hy- brid multi-objective partitioning algorithm, based on discrete particle swarm optimzation （DPSO） with local search strat- egy, called MDPSO-LS, is presented to solve the vlsi two- way partitioning with simultaneous cutsize and circuit delay minimization. Inspired by the physics of genetic algorithm, uniform crossover and random two-point exchange operators are designed to avoid the case of generating infeasible so- lutions. Furthermore, the phenotype sharing function of the objective space is applied to circuit partitioning to obtain a better approximation of a true Pareto front, and the theorem of Markov chains is used to prove global convergence. To improve the ability of local exploration, Fiduccia-Matteyses （FM） strategy is also applied to further improve the cutsize of each particle, and a local search strategy for improving circuit delay objective is also designed. Experiments on IS- CAS89 benchmark circuits show that the proposed algorithm is efficient.

关键词： vlsi physical design circuit partitioning par-ticle swarm optimization

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PWM vlsi Neural Network for Fault Diagnosis

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自动化学报 2005年第2期31卷 195-201页

作者：吕琛王桂增张泽宇 Department of Automation Tsinghua University Beijing 100084 Changchun Institute of Optics Fine Mechanics and Physics CAS Changchun 130031

An improved pulse width modulation (PWM) neural network vlsi circuit for fault diagnosis is presented, which differs from the software-based fault diagnosis approach and exploits the merits of neural network vlsi circuit. A simple synapse multiplier is introduced, which has high precision, large linear range and less switching noise effects. A voltage-mode sigmoid circuit with adjustable gain is introduced for realization of different neuron activation functions. A voltage-pulse conversion circuit required for PWM is also introduced, which has high conversion precision and linearity. These 3 circuits are used to design a PWM vlsi neural network circuit to solve noise fault diagnosis for a main bearing. It can classify the fault samples directly. After signal processing, feature extraction and neural network computation for the analog noise signals including fault information,each output capacitor voltage value of vlsi circuit can be obtained, which represents Euclid distance between the corresponding fault signal template and the diagnosing signal, The real-time online recognition of noise fault signal can also be realized.

关键词： PWM型 vlsi 神经网络故障诊断噪声脉冲宽度调节

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Improved FFSBM Algorithm and Its vlsi Architecture for AVS Video Standard

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Journal of Computer Science & Technology 2006年第3期21卷 378-382页

作者：张力解晓东吴迪 Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 P.R. China.Graduate University of Chinese Academy of Sciences Beijing 100039 P.R. China Graduate University of Chinese Academy of Sciences Beijing 100039 P.R. China Grandview Semiconductor (Beijing) Corporation Beijing 100039 P.R. China

The Video part of AVS （Audio Video Coding Standard） has been finalized recently. It has adopted variable block size motion compensation to improve its coding efficiency. This has brought heavy computation burden when it is applied to compress the HDTV （high definition television） content. Based on the original FFSBM （fast full search blocking matching）, this paper proposes an improved FFSBM algorithm to adaptively reduce the complexity of motion estimation according to the actual motion intensity. The main idea of the proposed algorithm is to use the statistical distribution of MVD （motion vector difference）. A vlsi （very large scale integration） architecture is also proposed to implement the improved motion estimation algorithm. Experimental results show that this algorithm-hardware co-design gives better tradeoff of gate-count and throughput than the existing ones and is a proper solution for the variable block size motion estimation in AVS.

关键词： AVS FFSBM motion estimation vlsi

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Nesterov’s Smoothing and Excessive Gap Methods for an Optimization Problem in vlsi Placement

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Journal of the Operations Research Society of China 2014年第4期2卷 423-443页

作者： Jian-Li Chen Yan Cui Wen-Xing Zhu Center for Discrete Mathematics and Theoretical Computer Science Fuzhou UniversityFuzhou 350108China

In this paper,we propose an algorithm for a nonsmooth convex optimization problem arising in very large-scale integrated circuit placement.The objective function is the sum of a large number of Half-Perimeter Wire Length(HPWL)functions and a strongly convex function.The algorithm is based on Nesterov’s smoothing and excessive gap techniques.The main advantage of the algorithm is that it can capture the HPWL information in the process of optimization,and every subproblem has an explicit solution in the process of optimization.The convergence rate of the algorithm is Oe1=k2T;where k is the iteration counter,which is optimal.We also present preliminary experiments on nine placement contest benchmarks.Numerical examples confirm the theoretical results.

关键词： vlsi Global placement Nonsmooth convex optimization Smoothing technique Excessive gap technique

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