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Design of Low Power transmission gate Based 9T SRAM Cell

Computers, Materials & Continua 2022年第7期72卷 1309-1321页

作者： S.Rooban Moru Leela Md.Zia Ur Rahman N.Subbulakshmi R.Manimegalai Department of Electronics and Communication Engineering Koneru Lakshmaiah Education FoundationVaddeswaramGunturAndhra Pradesh522502India Department of Electronics and Communication Engineering Francis Xavier Engineering CollegeTirunelveliTamil Nadu627003India Department of Computer Science and Engineering PSG Institute of Technology and Applied ResearchCoimbatoreTamil Nadu641062India

Considerable research has considered the design of low-power and high-speed *** integrated circuits with low-power consumption is an important issue due to the rapid growth of high-speed *** static random-access memory(SRAM)units are necessary components in fast mobile *** SRAM cells are more energyconsuming and with lower *** major constraints in SRAM cells are their reliability and low *** objectives of the proposed method are to provide a high read stability,low energy consumption,and better writing abilities.A transmission gate-based multi-threshold single-ended Schmitt trigger(ST)9T SRAM cell in a bit-interleaving structure without a write-back scheme is ***,an ST inverter with a single bit-line design is used to attain the high read stability.A negative assist technique is applied to alter the trip voltage of the single-ended ST *** multithreshold complementary metal oxide semiconductor(MTCMOS)technique is adopted to reduce the leakage power in the proposed single-ended TGST 9T SRAM *** proposed system uses a combination of standard and ST inverters,which results in a large read *** with the previous ST 9T,ST 11T,11T,10T,and 7T SRAM cells,the proposed cell is implemented in Cadence Virtuoso ADE with 45-nm CMOS technology and consumes 35.80%,42.09%,31.60%,12.54%,and 31.60%less energy for read operations and 73.59%,93.95%,92.76%,89.23%,and 85.78%less energy for write operations,respectively.

关键词： Bit-interleaving low power SRAM cell schmitt trigger transmission gate

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An Improved Power Efficient Clock Pulsed D Flip-flop Using transmission gate

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Journal of Electronic & Information Systems 2023年第1期5卷 26-35页

作者： B.Syamala M.Thamarai Electronics and Communication Engineering Sri Vasavi Engineering CollegeAP534101India

Recent digital applications will require highly efficient and high-speed gadgets and it is related to the minimum delay and power *** proposed work deals with a low-power clock pulsed data flip-flop(D flip-flop)using a transmission *** accomplish a power-efficient pulsed D flip-flop,clock gating is *** gated clock reduces the unnecessary switching of the transistors in the circuit and thus reduces the dynamic power *** clock gating approach is employed by using an AND gate to disrupt the clock input to the circuit as per the control signal called *** to this process,the clock gets turned off to reduce power consumption when there is no change in the *** proposed transmission gate-based pulsed D flip-flop’s performance with clock gating and without clock gating circuit is *** proposed pulsed D flip-flop power consumption is 1.586μw less than the without clock gated ***,the authors have designed a 3-bit serial-in and parallel-out shift register using the proposed D flip-flop and analyzed the *** Electronic Design Automation tool is used to simulate all the circuits with 45 nm technology.

关键词： Pulsed D flip-flop Clock gating Low power Shift register transmission gate

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An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending

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Frontiers of Information Technology & Electronic Engineering 2022年第6期23卷 950-965页

作者： Ayoub SADEGHI Nabiollah SHIRI Mahmood RAFIEE Mahsa TAHGHIGH Department of Electrical Engineering.ShirazBranch Islamic Azad UniversityShiraz 71987-74731Iran

We present a new counter-based Wallace-tree(CBW)8×8 *** multiplier’s counters are implemented with a new hybrid full adder(FA)cell,which is based on the transmission gate(TG)*** proposed FA,TG-based AND gate,and hybrid half adder(HA)generate M:3(4≤M≤7)digital counters with the ability to save at least 50%area *** by 90 nm technology prove the superiority of the proposed FA and digital counters under different conditions over the state-of-the-art *** using the proposed cells,the CBW multiplier exhibits high driving capability,low power consumption,and high *** CBW multiplier has a 0.0147 mm^(2)die area in a *** post-layout extraction proves the accuracy of experimental *** image blending mechanism is proposed,in which a direct interface between MATLAB and HSPICE is used to evaluate the presented CBW multiplier in image processing *** peak signal-to-noise ratio(PSNR)and structural similarity index metric(SSIM)are calculated as image quality parameters,and the results confirm that the presented CBW multiplier can be used as an alternative to designs in the literature.

关键词： Full adder transmission gate Counter Multiplier Three-dimensional layout Image blending

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A high speed low power low offset dynamic comparator used in SHA-less pipelined ADC

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Journal of Semiconductors 2014年第5期35卷 110-117页

作者：刘术彬朱樟明杨银堂刘帘曦 School of Microelectronics Xidian University

A novel fully differential high speed high resolution low offset CMOS dynamic comparator has been implemented in the SMIC 0.18 μm process used for a sample-and-hold amplifier （SHA）-less pipelined analog-to-digital converters （ADC）. Based on the analysis and optimization between delay time and offset, an enhanced reset architecture with transmission gate was introduced to speed up the comparison and reset procedure. Four inputs with two cross coupled differential pairs, reconstituted bias circuit for tail current transistor and common centroid layouts make the comparator more robust against mismatch and process variations. The simulation results demonstrate that the proposed design achieves 1 mV sensitivity at 2.2 GHz sampling rate with a power consumption of 510 μW, while the mean offset voltage is equal to 10.244 mV.

关键词： SHA-less ADC dynamic comparator high speed low offset low power transmission gate

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Leakage Analysis of a Low Power 10 Transistor SRAM Cell in 90 nm Technology

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Circuits and Systems 2016年第6期7卷 1033-1041页

作者： Parimaladevi Muthusamy Sharmila Dhandapani Department of Information and Communication Engineering Anna University Chennai India Department of Electronics and Instrumentation Engineering Bannari Amman Institute of Technology Sathyamangalam India

In this paper, a novel 10 Transistor Static Random Access Memory (SRAM) cell is proposed. Read and Write bit lines are decoupled in the proposed cell. Feedback loop-cutting with single bit line write scheme is employed in the 10 Transistor SRAM cell to reduce active power consumption during the write operation. Read access time and write access time are measured for proposed cell architecture based on Eldo SPICE simulation using TSMC based 90 nm Complementary Metal Oxide Semiconductor (CMOS) technology at various process corners. Leakage current measurements made on hold mode of operation show that proposed cell architecture is having 12.31 nano amperes as compared to 40.63 nano amperes of the standard 6 Transistor cell. 10 Transistor cell also has better performance in terms of leakage power as compared to 6 Transistor cell.

关键词： SRAM transmission gate Subthreshold Leakage gate Leakage Read Access Time Write Access Time

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