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timing error Aware Register Allocation in TS

Computer Systems Science & Engineering 2022年第1期40卷 273-286页

作者： Sheng Xiao Jing He Xi Yang Heng Zhou Yujie Yuan Information Science and Engineering Department Hunan First Normal UniversityChangsha410205China Computer School Wuhan UniversityWuhan430072China Department of Computer Science Kennesaw State UniversityKennesaw30144-5588USA Hunan Guangyi Experimental Middle School Changsha410205China

timing speculative(TS)architecture is promising for improving the energy efficiency of microprocessors.error recovery units,designed for tolerating occasional timing errors,have been used to support a wider range of voltage scaling,therefore to achieve a better energy efficiency.More specifically,the timing error rate,influenced mainly by data forwarding,is the bottleneck for voltage down-scaling in TS processors.In this paper,a new timing error Aware Register Allocation method is proposed.First,we designed the Dependency aware Interference Graph(DIG)construction to get the information of Read after Write(RAW)in programs.To build the construction,we get the disassemble code as input and suppose that there are unlimited registers,the same way as so-called virtual registers in many compilers.Then we change the disassemble codes to the SSA form for each basic block to make sure the registers are defined only once.Based on the DIG construction,registers were real-located to eliminate the timing error,by loosening the RAW dependencies.We con-struct the DIG for each function of the program and sort the edge of DIG by an increasing weight order.Since a smaller weighted-edge value means that its owner nodes have more frequent access in instruction flows,we expect it in different registers with no read-write dependency.At the same time,we make sure that there are no additional new spill codes emerging in our algorithm to minimize the rate of spill code.A high rate of spill code will not only decrease the performance of the system but also increase the unexpected read-write dependency.Next,we reallocate the reg-isters by weight order in turn to loosen the RAW dependencies.Furthermore,we use the NOP operation to pad the instructions with a minimal distance value of 2.Experiment results showed that the average distance of RAW dependencies was increased by over 20%.

关键词： timing error timing speculative architecture register allocation energy efficiency

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