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threshold logic based low-level vision sparse object features

International Journal of Intelligent Computing and Cybernetics 2016年第4期9卷 314-324页

作者： Nitha Thomas Joshin John Mathew Alex James Department of Research EnviewTrivandrumIndia ARS Traffic and Transport Technology TrivandrumIndia School of Engineering Nazarbayev UniversityAstanaKazakhstan

Purpose-The real-time generation of feature descriptors for object recognition is a challenging *** this research,the purpose of this paper is to provide a hardware friendly framework to generate sparse features that can be useful for key feature point selection,feature extraction,and descriptor *** inspiration is drawn from feature formation processes of the human brain,taking into account the sparse,modular,and hierarchical processing of visual ***/methodology/approach-A sparse set of neurons referred as active neurons determines the feature points necessary for high-level vision applications such as object recognition.A psycho-physical mechanism of human low-level vision relates edge detection to noticeable local spatial stimuli,representing this set of active neurons.A cognitive memory cell array-based implementation of low-level vision is *** of memory cell in edge detection are used for realizing human vision inspired feature selection and leading to feature vector construction for high-level vision ***-True parallel architecture and faster response of cognitive circuits avoid time costly and redundant feature extraction *** of proposed feature vector toward high-level computer vision applications is demonstrated using standard object recognition *** comparison against existing state-of-the-art object recognition features and methods shows an accuracy of 97,95,69 percent for Columbia Object Image Library-100,ALOI,and PASCAL VOC 2007 databases indicating an increase from benchmark methods by 5,3 and 10 percent,***/value-A hardware friendly low-level sparse edge feature processing system isproposed for recognizing *** edge features are developed based on threshold logic of neurons,and the sparse selection of the features applies a modular and hierarchical processing inspired from the human neural system.

关键词： Object recognition Object features Sparse features threshold logic Low-level vision Active neurons Cognitive memory-cell array Edge detection Feature description

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Energy Recovery threshold logic and Power Clock Generation Circuits

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Journal of Semiconductors 2004年第11期25卷 1403-1408页

作者：杨骞周润德清华大学微电子学研究所北京100084

Energy recovery threshold logic (ERTL) is proposed,which combines threshold logic with adiabatic *** achieves low energy as well as low gate complexity.A high efficiency power clock generator is also proposed,which can adjust duty cycle of MOS switch in power clock generator depending on logic complexity and operating frequency to achieve optimum energy ***-form results are derived,which facilitate efficiency-optimized design of the power clock *** ERTL PLA and a conventional PLA are designed and simulated on 0.35μm *** energy efficiency of the proposed power clock generator can reach 77%～85% operating between 20～*** results indicate that ERTL is a low energy *** power loss of power clock circuits,ERTL PLA still shows 65%～77% power savings compared to conventional PLA.

关键词： energy recovery low power power clock threshold logic CMOS circuits

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Design of Quaternary ECL Q Gate

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Journal of Computer Science & Technology 1991年第1期6卷 32-36页

作者：庄南 Ningbo Normal College Ningbo 315211

A new explanation of quaternary Q gate expression in Post algebra is given in this paper by using transmission function theory proposed in [1] and the quaternary ECL Q gate circuit is de- *** SPICE2 simulation to this circuit has confirmed that it has desired logical function and is totally compatible with various quaternary ECL circuits proposed before.

关键词： Computer Metatheory Many Valued logics Computer Metatheory threshold logic Computer Simulation logic Circuits, Emitter Coupled logic Devices Gates

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Energy Recovery Capacitance Coupling logic and Its Synthesis Methodology

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Journal of Semiconductors 2005年第7期26卷 1334-1339页

作者：杨骞周润德清华大学微电子学研究所北京100084

A novel energy recovery logic style ERCCL （energy recovery capacitance coupling logic） , which has good energy performance compared to the conventional CMOS logic and other advanced energy recovery logic, is proposed. ERCCL uses capacitance coupling to perform a logic function, so it can energy-efficiently implement a high fan-in complex logic in a single gate. ERCCL is also a type of threshold logic. The gate count of a system based on ERCCL can be significantly reduced,which,in turn,will decrease the energy loss. A threshold logic synthesis methodology for ERCCL is also presented. MCNC benchmarks are run through the proposed synthesis methodology. The results indicate that about an 80% reduction in gate count can be obtained when compared with the synthesis results of SIS.

关键词： energy recovery threshold logic logic synthesis capacitance coupling CMOS circuits

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Combined Linear-Nonlinear Control for Improved Dynamic Response of DC-DC Buck Converter 11th

Combined Linear-Nonlinear Control for Improved Dynamic Respo...

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2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology(ICSICT-2012)

作者： Xin Chen Ping Luo Shao-Wei Zhen State Key Laboratory of Electronic Thin Films and Integrated Devices University of Electronic Science and Technology of China

ISBN: (纸本)9781467324748

This paper presents linear-non linear control design and implementation method to achieve improved dynamic response of dc-dc buck *** implementation includes a threshold logic which is relatively simple and well suited for practical high frequency switched-mode power *** to the conventional dc-dc buck converters which only use linear control,the linear-nonlinear control（LnLc）is presented as a solution to improve dynamic ***,a buck converter with proposed structure is designed and simulated in a standard 65nm CMOS *** simulation results show the step-load transient response time is within 10us.

关键词： results response solution Solution Transient Response Time Dynamic response Solutions step-down converter linear control threshold logic proposed structure switched mode power supplies

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