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Short Tail:taming tail latency for erasure-code-based in-memory systems

Frontiers of Information Technology & Electronic Engineering 2022年第11期23卷 1646-1657页

作者： Yun TENG Zhiyue LI Jing HUANG Guangyan ZHANG College of Computer Science and Technology Jilin UniversityChangchun 130012China Department of Computer Science and Technology Tsinghua UniversityBeijing 100084China Key Laboratory of Symbolic Computation and Knowledge Engineering of Ministry of Education Jilin UniversityChangchun 130012China Beijing National Research Center for Information Science and Technology(Tsinghua University) Beijing 100084China

In-memory systems with erasure coding(EC)enabled are widely used to achieve high performance and data availability.However,as the scale of clusters grows,the server-level fail-slow problem is becoming increasingly frequent,which can create long tail latency.The influence of long tail latency is further amplified in EC-based systems due to the synchronous nature of multiple EC sub-operations.In this paper,we propose an EC-enabled in-memory storage system called ShortTail,which can achieve consistent performance and low latency for both reads and writes.First,ShortTail uses a lightweight request monitor to track the performance of each memory node and identify any fail-slow node.Second,ShortTail selectively performs degraded reads and redirected writes to avoid accessing fail-slow nodes.Finally,ShortTail posts an adaptive write strategy to reduce write amplification of small writes.We implement ShortTail on top of Memcached and compare it with two baseline systems.The experimental results show that ShortTail can reduce the P99 tail latency by up to 63.77%;it also brings significant improvements in the median latency and average latency.

关键词： Erasure code In-memory system Node fail-slow small write Tail latency

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Design and Implementation of Hierarchy Cache Using Pagefile

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Wuhan University Journal of Natural Sciences 2004年第6期9卷 890-894页

作者： XIEChang-sheng LIURui-fang TANZhi-hu CollegeofComputerScienceandTechnology HuazhongUniversityofScienceandTechnologyWuhan430074HubeiChina

This paper presents a novel hierarchy cache architecture for the purpose of optimizing IO performance. The main idea of the hierarchy cache is to use a few megabytes of RAM and a pagefile to form a two-level cache architecture, The pagefile is equivalent to the cache disk in DCD (Disk Caching Disk). The pagefile outperforms data disks, because data are accessed in different units and different ways. small writes are collected in the RAM cache first, and data will be transferred to the pagefile in large writes later. When the system is idle, it will destage data from the pagefile to data disks. The performance test results show that the hierarchy cache can improve IO performance dramatically for small writes, and the mail server using the hierarchy cache driver can handle transactions about 2.2 times faster than the normal mail server. The hierarchy cache is implemented as a filter driver, so it's transparent to the current Windows 2000/ Windows XP operating system. Key words hierarchy cache - pagefile - small write - disk caching disk - filter driver CLC number TP 311 Foundation item: Supported by the National Natural Science Foundation of China (60273073)Biography: XIE chang-sheng (1945-), male Professor, research direction: storage system, network storage.

关键词： hierarchy cache pagefile small write disk caching disk filter driver

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