检索结果-南通市图书馆

A low noise high efficiency buck DC-DC converter with sigma-delta modulation

Journal of Semiconductors 2011年第7期32卷 81-88页

作者：蔡曙江皮常明严伟李文宏 State Key Laboratory of ASIC & Systems Fudan University

Some research efforts to improve the efficiency and noise performance of buck DC-DC converters are explored.A carefully designed power MOSFET driver,including a dead time controller,discontinuous current mode（DCM） controller and gate width controller,is proposed to improve *** of PWM modulation, sigma-delta modulation is introduced into the feedback loop of the converter to move out the clock-referred harmonic *** proposed converter has been designed and fabricated by a 0.35μm CMOS *** results show that the peak efficiency of the converter can reach 93%and sigma-delta modulation suppresses the harmonic spike by 30 dB over PWM modulation.

关键词： buck DC-DC converter PWM modulation sigma-delta modulation DCM dead time control width control current sensing

来源：

维普期刊数据库

同方期刊数据库评论

在线全文

学校读者我要写书评

暂无评论

A Multi-Channel CMOS Analog Front-End Interface IC with 157.8 d B Current Detection Dynamic Range

引用

Chinese Journal of Electronics 2024年第2期33卷 393-402页

作者： Kunyu WANG Wenjing XU Chengbin ZHANG Yanjun YANG Man-Kay LAW Li ZHOU Jie CHEN Ming CHEN Institute of Microelectronics of the Chinese Academy of Science University of Chinese Academy of Sciences Zunyi Normal University Institute of Microelectronics and Dept.of ECE FST University of Macau

A high dynamic range and low-noise CMOS(complementary metal-oxide-semiconductor transistor)front-end interface integrated circuit(IC) with multi-channel detection is presented in this paper. Two different current detection channels, composed of a trans-impedance amplifier(TIA) and an integrator-differentiator TIA, are used to boost the current detection range. A capacitance-coupled instrument amplifier(CCIA) is also included to realize high precision voltage detection. A fourth-order sigma-delta modulator using a second-order loop filter and a second-order noise shaping integral quantizer is adopted to realize effective number of bits above 16 bits. The presented interface IC is implemented in 0.18-μm CMOS process with supply voltage of 3.3 V, and a proto-type electrochemical sensor platform with miniaturized sensor array is developed to verify the functionality of the interface IC. Measurement results indicate that the designed interface IC achieves 157.8 d B current detection dynamic range, and the measured input-referred current noise and voltage noise floor are 1.04 p A and 58.4 n V within 10 k Hz integration bandwidths,respectively.

关键词： Integrated circuits sigma-delta modulation Semiconductor device measurement Voltage measurement Current measurement Noise Bandwidth

来源：

同方期刊数据库评论

在线全文

同方期刊数据库

学校读者我要写书评

暂无评论

A 1-V 60-μW 85-dB dynamic range continuous-time third-order sigma-delta modulator

引用

Journal of Semiconductors 2009年第12期30卷 118-122页

作者：李渊文齐达董一枫许俊任俊彦 State Key Laboratory of ASIC & System Micro-Nanoelectronics Science and Technology Innovation Platform Fudan University

A 1-V third order one-bit continuous-time（CT） EA modulator is presented. Designed in the SMIC mixedsignal 0.13-μm CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficient circuit design methodology for the CT ZA modulator is proposed and verified. Low power dissipation is achieved through the use of two-stage class A/AB amplifiers. The presented modulator achieves 81.4-dB SNDR and 85-dB dynamic range in a 20-kHz bandwidth with an over sampling ratio of 128. The total power consumption of the modulator is only 60 μW from a 1-V power supply and the prototype occupies an active area of 0.12 mm^2.

关键词： analog-to-digital converter continuous-time filter low-power low-voltage sigma-delta modulation

来源：

维普期刊数据库

同方期刊数据库评论

在线全文

学校读者我要写书评

暂无评论

A 4 GHz CMOS multiplier for sigma–delta modulated signals

引用

Journal of Semiconductors 2014年第1期35卷 91-95页

作者：郭晓丹孟桥梁勇 Institute of RF- & OE-ICs Southeast University Engineering Research Center of RF-ICs & RF-Systems Ministry of Education

An integrated circuit design of a high speed multiplier for direct sigma-delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its sub-modules and works efficiently at a high speed. The multiplier＇s stability has also been improved with source coupled logic technology. The chip is fabricated in a TSMC 0.18-μm CMOS process. The test results demonstrate that the chip realizes the multiplication function and exhibits an excellent performance. It can work at 4 GHz and the voltage output amplitude reaches the designed maximum value with no error bit caused by logic race-and-hazard. Additionally, the analysis of the multiplier＇s noise performance is also presented.

关键词： CMOS sigma-delta modulation multiplier bit-stream

来源：

维普期刊数据库

同方期刊数据库评论

在线全文

学校读者我要写书评

暂无评论

欢迎您,

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

在线全文

在线全文

在线全文

在线全文

请选择保存的检索档案：

请选择收藏分类：

通借通还

欢迎您,

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

在线全文

在线全文

在线全文

在线全文

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：