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A strained Si-channel NMOSFET with low field mobility enhancement of about 140% using a sige virtual substrate

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Journal of Semiconductors 2012年第9期33卷 65-68页

作者：崔伟唐昭焕谭开洲张静钟怡胡辉勇徐世六李平胡刚毅 State Key Laboratory of Electronic Thin Films and Integrated Devices UESTCChengdu 610023China Science and Technology on Analog Integrated Circuit Laboratory Chongqing 400060China Key Laboratory of the Ministry of Education for Wide-Band Gap Semiconductor Materials and Devices Microelectronics SchoolXidian UniversityXi'an 710071China

A fully standard CMOS integrated strained Si-channel NMOSFET has been demonstrated. By adjusting the thickness of graded sige, modifying the channel doping concentration, changing the Ge fraction of the relaxed sige layer and forming a p-well by multiple implantation technology, a surface strained Si-channel NMOSFET was fabricated, of which the low field mobility was enhanced by 140%, compared with the bulk-Si control device. Strained NMOSFET and PMOSFET were used to fabricate a strained CMOS inverter based on a sige virtual substrate. Test results indicated that the strained CMOS converter had a drain leakage current much lower than the Si devices, and the device exhibited wonderful on/off-state voltage transmission characteristics.

关键词： CMOS inverter strained Si mobility enhancement sige virtual substrate relaxed layer

Fabrication and Characterization of Strained Si Material Using sige virtual substrate for High Mobility Devices

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Journal of Semiconductors 2007年第10期28卷 1518-1522页

作者：梁仁荣张侃杨宗仁徐阳王敬许军清华大学微电子学研究所北京100084

The fabrication and characterization of strained-Si material grown on a relaxed Si0.79 Ge0.21/graded Si1-x- Gex/Si virtual substrate, using reduced pressure chemical vapor deposition, are presented. The Ge concentration of the constant composition sige layer and the grading rate of the graded sige layer are estimated with double-crystal X-ray diffraction and further confirmed by SIMS measurements. The surface root mean square roughness of the strained Si cap layer is 2.36nm,and the strain is about 0.83% as determined by atomic force microscopy and Raman spectra, respectively. The threading dislocation density is on the order of 4 × 10^4cm^-2. Furthermore, it is found that the stress in the strained Si cap layer is maintained even after the high thermal budget process, nMOSFET devices are fabricated and measured in strained-Si and unstrained bulk-Si channels. Compared to the co-processed bulk-Si MOSFETs at room temperature,a significant low vertical field mobility enhancement of about 85% is observed in the strained-Si devices.

关键词： strained Si RPCVD sige virtual substrate mobility enhancement

Fabrication of High Quality sige virtual substrates by Combining Misfit Strain and Point Defect Techniques

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Tsinghua Science and Technology 2009年第1期14卷 62-67页

作者：梁仁荣王敬许军 Tsinghua National Laboratory for Information Science and Technology (TNList) Institute of Microelectronics Tsinghua University

High quality strain-relaxed thin sige virtual substrates have been achieved by combining the misfit strain technique and the point defect technique. The point defects were first injected into the coherently strained sige layer through the ＂inserted Si layer＂ by argon ion implantation. After thermal annealing, an in- termediate sige layer was grown with a strained Si cap layer. The inserted Si layer in the sige film serves as the source of the misfit strain and prevents the threading dislocations from propagating into the next epitaxial layer. A strained-Silsigelinserted-Silsige heterostructure was achieved with a threading dislocation density of 1×10^4 cm-2 and a root mean square surface roughness of 0.87 nm. This combined method can effectively fabricate device-quality sige virtual substrates with a low threading dislocation density and a smooth surface.

关键词： strain relaxation point defects misfit strain sige virtual substrate strained Si inserted Si layer

Growth of strained-Si material using low-temperature Si combined with ion implantation technology

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Journal of Semiconductors 2010年第6期31卷 12-15页

作者：杨洪东于奇王向展李竞春宁宁杨谟华 State Key Laboratory of Electronic Thin Films and Integrated Devices University of Electronic Science and Technology

In order to fabricate strained-Si MOSFETs,we present a method to prepare strained-Si material with highquality surface and ultra-thin sige virtual *** sandwiching a low-temperature Si（LT-Si） layer between a Si buffer and a pseudomorphic Si_（0.8）Ge_（0.2） layer,the surface roughness root mean square（RMS） is 1.02 nm and the defect density is 10~6 cm^（-2） owing to the misfit dislocations restricted to the LT-Si layer and the threading dislocations suppressed from penetrating into the Si_（0.8）Ge_（0.2） *** employing P~＋ implantation and rapid thermal annealing, the strain relaxation degree of the Si_（0.8）Ge_（0.2） layer increases from 85.09%to 96.41%and relaxation is more uniform. Meanwhile,the RMS（1.1nm） varies a little and the defect density varies *** to the results,the method of combining an LT-Si layer with ion implantation can prepare high-quality strained-Si material with a high relaxation degree and ultra-thin sige virtual substrate to meet the requirements of device applications.

关键词： low-temperature silicon strained silicon ion implantation sige virtual substrate