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Application of source biasing technique for energy efficient DECODER circuit design: memory array application

Journal of Semiconductors 2018年第4期39卷 49-54页

作者： Neha Gupta Priyanka Parihar Vaibhav Neema Department of Electronics and Telecommunication Engineering Institute of Engineering and Technology Devi Ahilya University

Researchers have proposed many circuit techniques to reduce leakage power dissipation in memory cells. If we want to reduce the overall power in the memory system, we have to work on the input circuitry of memory architecture i.e. row and column decoder. In this research work, low leakage power with a high speed row and column decoder for memory array application is designed and four new techniques are proposed. In this work, the comparison of cluster DECODER, body bias DECODER, source bias DECODER, and source coupling DE- CODER are designed and analyzed for memory array application. Simulation is performed for the comparative analysis of different DECODER design parameters at 180 nm GPDK technology file using the CADENCE tool. Simulation results show that the proposed source bias DECODER circuit technique decreases the leakage current by 99.92% and static energy by 99.92% at a supply voltage of 1.2 V. The proposed circuit also improves dynamic power dissipation by 5.69%, dynamic PDP/EDP 65.03% and delay 57.25% at 1.2 V supply voltage.

关键词： SRAM leakage current delay sleep transistor

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Ground bounce noise reduction aware combinational multi threshold CMOS circuits for nanoscale CMOS multiplier

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Frontiers of Optoelectronics 2013年第3期6卷 327-337页

作者： Bipin Kumar VERMA Shyam Babu SINGH Shyam AKASHE Department of Electronics and Communication Engineering ITM University Gwalior (M.P.) 474001 India

Multi-threshold complementary metal-oxide- semiconductor （MTCMOS） is ofbn used to reduce the leakage current in idle circuit. Ground bounce noise produced during a transition mode （sleep-to-active） is an important challenge in MTCMOS. In this paper, various noise-aware combinational MTCMOS circuit was used to evaluate the ground bounce noise. An intermediate mode was applied in the sleep-to-active mode transition to reduce the charge stored on virtual lines to real ground. The dependence of ground bounce noise on voltage, transistor size and temperature was investigated with different MTCMOS circuit technique. The peak amplitude of ground bounce noise was reduced up to 78.82%. The leakage current of the circuit was decreased up to 99.73% and the active power of the circuit was reduced up to 62.32%. Simulation of multiplier with different MTCMOS circuit techniques was performed on 45nm CMOS technology.

关键词： multi-threshold complementary metal-oxide-semiconductor （MTCMOS） mode transition groundbounce noise sleep transistor

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