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Time-domain analysis methodology for large-scale rlc circuits and its applications

Science in China(Series F) 2006年第5期49卷 665-680页

作者： LUO Zuying CAI Yici Sheldon X.-D Tan HONG Xianlong WANG Xiaoyi PAN Zhu FU Jingjing Department of Computer Science and Technology Tsinghua University Beijing 100084 China College of Information Science and Technology Beijing Normal University Beijing 100875 China Department of Electrical Engineering University of California at Riverside Riverside CA92521 USA

With soaring work frequency and decreasing feature sizes, VLSI circuits with rlc parasitic components are more like analog circuits and should be carefully analyzed in physical design. However, the number of extracted rlc components is typically too large to be analyzed efficiently by using present analog circuit simulators like SPICE. In order to speedup the simulations without error penalty, this paper proposes a novel methodology to compress the time-descritized circuits resulted from numerical integration approximation at every time step. The main contribution of the methodology is the efficient structure-level compression of DC circuits containing many current sources, which is an important complement to present circuit analysis theory. The methodology consists of the following parts： 1） An approach is proposed to delete all intermediate nodes of RL branches. 2） An efficient approach is proposed to compress and back-solve parallel and serial branches so that it is error-free and of linear complexity to analyze circuits of tree topology. 3） The Y to πtransformation method is used to error-free reduce and back-solve the intermediate nodes of ladder circuits with the linear complexity. Thus, the whole simulation method is very accurate and of linear complexity to analyze circuits of chain topology. Based on the methodology, we propose several novel algorithms for efficiently solving rlc-model transient power/ground （P/G） networks. Among them, EQU-ADI algorithm of linear-complexity is proposed to solve rlc P/G networks with mesh-tree or mesh-chain topologies. Experimental results show that the proposed method is at least two orders of magnitude faster than SPICE while it can scale linearly in both time- and memory-complexity to solve very large P/G networks.

关键词： rlc circuits analog circuit analysis time-domain analysis PIG networks algorithm complexity

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A Programmable Pre-emphasis Technique with Combined rlc Source Degeneration for High-Speed Serial Link Transmitters

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Chinese Journal of Electronics 2022年第1期31卷 52-58页

作者： WANG Tonghui ZOU Jiaxuan QI Huanhuan WANG Xi WANG Jingbo ZHANG Hong School of Microelectronics Xi'an Jiaotong University No.58 Research Institute China Electronic Technology Group Corporation

This paper presents a clock-less programmable pre-emphasis technique realized by a driver with combined resistive-inductive-capacitive source degeneration for high-speed serial link transmitters. The addition of a series inductive-capacitive resonance network expands the bandwidth of the driver without lowering down the pre-emphasis gain. The driver with the proposed preemphasis technique provides adjustable gain from mid-frequency to high-frequency which is controlled by a tunable tail current, offering the capability for the transmitter to adapt to different cable loss from 0 to 6 d B. The driver has been employed in a 2:4 multiplexing and cable driving integrated circuit for 1.65 Gbps high-definitionmultimedia-interface and digital-visual-interface application to drive up to 7 m 24-American-wire-gauge *** in 180 nm Si Ge Bi CMOS technology, the transmitter consumes 68.6 m W for 6 d B pre-emphasis under 3.3 V power supply.

关键词： rlc circuits high-speed serial link transmitters SiGe BiCMOS technology multiplexing equipment BiCMOS integrated circuits driver circuits pre-emphasis gain Ge-Si alloys high-definition-multimedia-interface combined rlc source degeneration series inductive-capacitive resonance network transmitter resistive-inductive-capacitive source degeneration programmable pre-emphasis technique transmitters digital-visual-interface application

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